DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-16 remain pending in this application. Acknowledgement is made of the amendment received 02/03/2026. Claims 17-20 are canceled, claims 1 and 14 are amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14, the terms “nano-scale device” and “micro-scale device” in claim 14 are relative terms which renders the claim indefinite. The terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, the boundary at which a device is considered “nano-scale” vs “micro-scale” is unclear, and the claims nor specification provide no standard for ascertaining a measurable boundary. Therefore, absent a definitive boundary, one of ordinary skill in the art cannot determine the metes and bounds of the claim.
For the purpose of compact prosecution, the Examiner interprets the claim to mean “wherein a width of the second gate is less than a width of the first gate”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 6-9, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN 102184871 A, English translation of description provided in previous office action, as cited in IDS dated 08/25/2025, hereafter Liu) in view of Vogt et al (US 20150235864 A1, hereafter Vogt) and Huang et al (US 7521304 B1, hereafter Huang).
Regarding claim 1, Liu teaches: A method of manufacturing a semiconductor device structure (Liu figs 4-7, ¶0062-0068), the method comprising:
a) forming a first gate dielectric layer (Liu 307, ¶0062, “oxide”) on a first region (Liu 302) of a semiconductor substrate (Liu 300)(Liu fig 4), and forming a second gate dielectric layer (Liu 308, ¶0062, “oxide”) on a second region (Liu 301) of the semiconductor substrate (Liu fig 4, ¶0062-0063);
b) forming a conductive layer (Liu ¶0064, “forming a polysilicon layer”, applicant discloses that suitable materials for a conductive layer includes “polysilicon”, spec ¶0011) on the first gate dielectric layer and the second gate dielectric layer (Liu fig 5, ¶0064, “etching the polysilicon layer … by dry etching method … remaining polysilicon layer … form the gate 309”, the polysilicon layer must at least be formed on both 307 and 308 for etching to persist gate 309 on 307 and 308 respectively);
c) forming a barrier layer (Liu ¶0064, “forming … silicon nitride layer”, silicon nitride layer forms barrier layer 310) on the conductive layer (Liu fig 5, ¶0064);
d) patterning the barrier layer to form a barrier pattern (Liu fig 5, ¶0064, “etching the polysilicon layer and the silicon nitride layer by dry etching method after the patterning”, under a broadest reasonable interpretation, it appears that the silicon nitride layer is patterned to form a mask for subsequent dry etching);
e) etching the conductive layer (Liu fig 5, ¶0064, “etching the polysilicon layer”) to simultaneously form a first gate (Liu 309 within 302) and a second gate (Liu 309 within 301) by using the barrier pattern as a mask (Liu fig 5, ¶0064, “… silicon nitride layer … form … hard mask”)(Liu ¶0062-0064, fig 4, 5, a single step dry etch of the polysilicon layer simultaneously forms both gates in regions 302 and 301 within the same operation);
f) forming a photolithography pattern (Liu 313) on the semiconductor substrate (Liu fig 6, ¶0065), wherein the photolithography pattern has an implantation window (Liu fig 7, “ion implantation position”, under a broadest reasonable interpretation, the discontinuity in 313 of fig 7 is at least a window) that exposes a well implantation area (Liu 304, ¶0068) of the first region and a portion of the barrier pattern on the first gate (Liu fig 6, ¶0066-0067);
g) forming a well region (Liu 311, 312, ¶0067-0068, under a broadest reasonable interpretation, forms at least a P-well by ion implantation by boron and comprises a channel region 320, similar to applicant ¶0019) in the well implantation area by an ion implantation process using the lithography pattern and the exposed barrier pattern as masks (Liu fig 7, ¶0066, “gate barrier layer 310 … has a certain barrier effect so as to avoid damage to the polysilicon gate 309”, ¶0067, “photoresist 313 as a mask and the gate barrier layer 310”);
h) removing the photolithography pattern and the barrier pattern (Liu fig 8); and
i) forming a power device (Liu “LDMOS”, “power device”, ¶0003, 0069, 0079, fig 8) in the first region (Liu 302) based on the first gate (Liu 309 within 302)(Liu ¶0068, 0069, 0079, fig 8); and forming a high-density device (Liu “CMOS”, fig 8, applicant discloses that suitable materials for a high-density device includes CMOS devices, spec ¶0022) in the second region (Liu 301) based on the second gate (Liu 309 within 301)(Liu ¶0069, 0079, fig 8).
Liu does not explicitly teach: wherein the barrier layer is configured as an amorphous carbon barrier layer, and wherein a width of the second gate is less than or equal to 90 nanometers.
Vogt, in the same field of endeavor of semiconductor device manufacturing, teaches: a barrier layer (Vogt 104, 106, ¶0017, 0046, 0047, “referred to as carbon mask, carbon mask layer, carbon hard mask, or carbon hard mask layer”, “amorphous carbon layers”, similar to Liu 310) comprises an amorphous carbon barrier layer (Vogt 104, ¶0047, “amorphous carbon layers”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Liu to include the amorphous carbon barrier layer of Vogt to the barrier layer of Liu, and such that “the barrier layer is configured as an amorphous carbon barrier layer”, in order to reduce a feature size and/or a lateral dimension during subsequent processing (Vogt ¶0027).
Liu iv view of Vogt does not explicitly teach: wherein a width of the second gate is less than or equal to 90 nanometers.
Huang, in the same field of endeavor of semiconductor device manufacturing, teaches: a width of a gate (Huang 30, Col 4, Lines 1-7) is less than or equal to 90 nanometers (Huang “width of … 30 and 50 nanometers”, Col 4, Lines 10-14).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Liu in view of Vogt with the teaching of Huang, such that “a width of the second gate is less than or equal to 90 nanometers”, in order to form gates with reduced spacing, thereby allowing smaller transistors, improving speed, reducing power, and/or to increase transistor density of the device (Huang Col 2, Lines 3-14).
Further, the adjustment of a gate width is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a gate width is disclosed by Huang, and therefore discovering the optimum or working range of " a width of the second gate is less than or equal to 90 nanometers " involves only routine skill in the art.
Regarding claim 6, Liu in view of Vogt and Huang teaches: The method of claim 1.
Liu in view of Vogt and Huang does not explicitly teach: wherein the barrier layer has a high etching selectivity relative to the conductive layer.
Huang further teaches: adjusting etch selectivity of a barrier layer (Huang 60, Col 7, Lines 21-25, layer 60 is used as a mask, and is therefore at least capable of being a barrier layer) relative to a conductive layer (Huang 50, Col 4, Line 63 – Col 5, Line 4)(Huang Col 6, Lines 27-37).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the selectivity of the barrier and/or conductive layers of the method of Liu in view of Vogt and Huang, such that “the barrier layer has a high etching selectivity relative to the conductive layer”, as taught by Huang, in order to reduce the thickness of the barrier layer, thereby allowing for increased manufacturing efficiency by eliminating unnecessary material use (Huang Col 6, Lines 33-37).
Further, the adjustment of a layer etch selectivity is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a etch selectivity is disclosed by Huang, and therefore discovering the optimum or working range of "the barrier layer has a high etching selectivity relative to the conductive layer" involves only routine skill in the art.
Regarding claim 7, Liu in view of Vogt and Huang teaches: The method of claim 1, wherein the barrier layer (Liu 310 as modified to include Vogt 104) comprises an amorphous carbon barrier layer (Vogt 104, ¶0047, “amorphous carbon layers”) having at least one of diamond-like, graphite-like, or materials with properties ranging between diamond-like or graphite-like (Vogt ¶0047, 0054, “graphite-like carbon and/or diamond or diamond-like carbon”).
Regarding claim 8, Liu in view of Vogt and Huang teaches: The method of claim 7, wherein the amorphous carbon barrier layer (Liu 310 as modified to include Vogt 104) is formed on the conductive layer (Liu 309) by an atomic layer deposition process (Vogt ¶0111, “forming the carbon layer 104 may include … atomic layer deposition”)(Liu fig 5, ¶0064).
Regarding claim 9, Liu in view of Vogt and Huang teaches: The method of claim 7, wherein the amorphous carbon barrier layer (Liu 310 as modified to include Vogt 104) is a laminated structure comprising diamond-like and graphite-like materials (Vogt ¶0047, 0054) through one-time lamination or multiple times alternating lamination (Vogt ¶0106, by depositing of Vogt 104 onto the conductive layer of Liu, similar to Liu 309, Vogt 104 is united to another layer, and therefore meets a broadest reasonable interpretation of a “laminated structure”, where a common definition of a laminate is “to unite (layers of material) by an adhesive or other means” (for completeness of the record, https://www.merriam-webster.com/dictionary/laminate), therefore Liu in view of Vogt at least teaches “wherein the amorphous carbon barrier layer is a laminated structure comprising diamond-like and graphite-like materials through one-time lamination”, and therefore meets the claim).
Regarding claim 13, Liu in view of Vogt and Huang teaches: The method of claim 1, wherein a width of the first gate (Liu 309 within 302) is greater than a width of the second gate (Liu 309 within 301)(Liu fig 8).
Regarding claim 14, Liu in view of Vogt and Huang teaches: The method of claim 1, wherein the high-density device (Liu 309 in 301, as modified by Huang) is configured as a nano-scale device, and the power device (Liu 309 in 302) is configured as a micro-scale device (as best understood to mean “wherein a width of the second gate is less than a width of the first gate”, Liu fig 8).
Regarding claim 15, Liu in view of Vogt and Huang teaches: The method of claim 1, further comprising:
a) forming a power device (Liu “LDMOS”, “power device”, ¶0003, 0069, 0079, fig 8) in the first region (Liu 302) based on the first gate (Liu 309 within 302) and the well region (Liu 311, 312)(Liu ¶0068, 0069, 0079, fig 8); and
b) forming a high-density device (Liu “CMOS”, fig 8, applicant discloses that suitable materials for a high-density device includes CMOS devices, spec ¶0022) in the second region (Liu 301) based on the second gate (Liu 309 within 301)(Liu ¶0069, 0079, fig 8).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN 102184871 A, English translation of description provided in previous office action, as cited in IDS dated 08/25/2025, hereafter Liu) in view of Vogt et al (US 20150235864 A1, hereafter Vogt) and Huang et al (US 7521304 B1, hereafter Huang), as applied to claim 1 above, and further in view of Kim et al (US 20070148885 A1, hereafter Kim).
Regarding claim 2, Liu in view of Vogt and Huang teaches: The method of claim 1.
Liu in view of Vogt and Huang does not teach: wherein the patterning the barrier layer to form a barrier pattern comprises:
a) forming a photoresist layer on the barrier layer;
b) patterning the photoresist layer to form a patterned photoresist layer; and
c) etching the barrier layer to form the barrier pattern by using the patterned photoresist layer as a mask.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: patterning a barrier layer (Kim 25, ¶0038) to form a barrier pattern (Kim 25A), comprising:
a) forming a photoresist layer (Kim 27, ¶0022) on the barrier layer (Kim ¶0022, fig 2A);
b) patterning the photoresist layer to form a patterned photoresist layer (Kim ¶0022); and
c) etching the barrier layer to form the barrier pattern by using the patterned photoresist layer as a mask (Kim fig 2B, ¶0023).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the steps of Kim in the method of Liu in view of Vogt and Huang in order to use a denser material as a barrier layer, thereby allowing selective etching while reducing implantation of an impurity to a lower structure (Kim ¶0020), and/or in order to prevent generation of defective patterns (Kim ¶0038).
Regarding claim 3, Liu in view of Vogt, Huang, and Kim teaches: The method of claim 2.
Liu in view of Vogt, Huang, and Kim does not explicitly teach: wherein the etching the barrier layer to form the barrier pattern comprises using an oxygen plasma process.
Kim further teaches: using oxygen plasma etching to remove a barrier layer (Kim 25A)(Kim ¶0027).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Liu in view of Vogt, Huang, and Kim to use oxygen plasma etching to form the barrier pattern in order to simultaneously form the barrier pattern and remove the patterned photoresist layer (Kim ¶0023, 0024, 0027), and/or to ensure easy removal of the barrier layer outside the photoresist pattern by selective etching (Kim ¶0024, 0027).
Regarding claim 4, Liu in view of Vogt, Huang, and Kim teaches: The method of claim 2, wherein by setting the thickness of the photoresist layer, the patterned photoresist layer (Kim 27, ¶0022) is fully etched and removed when the etching process of the barrier layer (Liu 310 as modified by Kim 25A) is completed (Kim ¶0023).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN 102184871 A, English translation of description provided in previous office action, as cited in IDS dated 08/25/2025, hereafter Liu) in view of Vogt et al (US 20150235864 A1, hereafter Vogt) and Huang et al (US 7521304 B1, hereafter Huang), as applied to claim 1 above, and further in view of Bernacki et al (US 4436584 A, hereafter Bernacki).
Regarding claim 5, Liu in view of Vogt and Huang teaches: The method of claim 1, wherein the conductive layer comprises a polysilicon layer (Liu ¶0064, “polysilicon layer”), and the conductive layer is etched by a dry etching process to form a first gate (Liu 309 within 302) and a second gate (Liu 309 within 301).
Liu in view of Vogt and Huang does not explicitly teach: a reactive ion etching process.
Bernacki, in the same field of endeavor of semiconductor device manufacturing, teaches: using reactive ion etching for dry etching (Bernacki Col 1, Lines 39-47).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Liu in view of Vogt and Huang to use a reactive ion etching process to etch the conductive layer, in order to reduce undercutting or lateral etching of the conductive layer (Bernacki Col 1, Lines 39-47).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN 102184871 A, English translation of description provided in previous office action, as cited in IDS dated 08/25/2025, hereafter Liu) in view of Vogt et al (US 20150235864 A1, hereafter Vogt) and Huang et al (US 7521304 B1, hereafter Huang), as applied to claim 1 above, and further in view of Peng et al (US 20170018430 A1, hereafter Peng) and Kim et al (US 20070148885 A1, hereafter Kim).
Regarding claim 10, Liu in view of Vogt and Huang teaches: The method of claim 1.
Liu in view of Vogt and Huang does not explicitly teach: wherein a thickness of the conductive layer is in a range from 1000 angstroms to 2500 angstroms, and a thickness of the barrier layer is in a range from 2500 angstroms to 4000 angstroms.
Peng, in the same field of endeavor of semiconductor device manufacturing, teaches: wherein a thickness of a conductive layer (Peng ¶0038, “gate conductor 108”, formed from polysilicon layer 104, similar to Liu 309) is in a range from 1000 angstroms to 3000 angstroms (Peng ¶0021, “The thickness of polysilicon layer 104 can be between about 1000 Å and about 3000 Å, such as about 2000 Å”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust a thickness of the conductive layer of Liu in view of Vogt and Huang, such that “a thickness of the conductive layer is in a range from 1000 angstroms to 2500 angstroms”, in order to balance line width and connection resistance between gates in separate regions (Peng ¶0015), and/or in order to achieve a desired performance of the conductive layer.
Further, the adjustment of a layer thickness is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a conductive layer thickness is disclosed by Peng, and therefore discovering the optimum or working range of "a thickness of the conductive layer is in a range from 1000 angstroms to 2500 angstroms" involves only routine skill in the art.
Liu in view of Vogt, Huang, and Peng does not explicitly teach: a thickness of the barrier layer is in a range from 2500 angstroms to 4000 angstroms.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting a thickness of a barrier layer (Kim 25, ¶0038) is greater than 1000 angstroms (Kim ¶0020).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust a thickness of the barrier layer of Liu in view of Vogt, Huang, and Peng, such that “a thickness of the barrier layer is in a range from 2500 angstroms to 4000 angstroms”, in order to ensure impurities are less likely to penetrate layers below the barrier layer (Kim ¶0020).
Further, the adjustment of a layer thickness is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a barrier layer thickness is disclosed by Kim, and therefore discovering the optimum or working range of "a thickness of the barrier layer is in a range from 2500 angstroms to 4000 angstroms" involves only routine skill in the art.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN 102184871 A, English translation of description provided in previous office action, as cited in IDS dated 08/25/2025, hereafter Liu) in view of Vogt et al (US 20150235864 A1, hereafter Vogt) and Huang et al (US 7521304 B1, hereafter Huang), as applied to claim 1 above, and further in view of Peng et al (US 20170018430 A1, hereafter Peng).
Regarding claim 11, Liu in view of Vogt and Huang teaches: The method of claim 1.
Liu in view of Vogt and Huang does not explicitly teach: after the forming the barrier layer on the conductive layer, forming an anti-reflective layer on the barrier layer.
Peng, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: after forming a barrier layer (Peng ¶0038, “a nitride layer (e.g., SiNx)”, similar to Liu 310) on a conductive layer (Peng ¶0038, “gate conductor 108”, formed from polysilicon layer 104, similar to Liu 309)(Peng ¶0038), forming an anti-reflective layer (Peng 106) on the barrier layer (Peng fig 1E, ¶0023, 0038).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Liu in view of Vogt and Huang to include forming an anti-reflective layer on the barrier layer, as taught by Peng, in order to reduce reflectivity of underlying layers, thereby decreasing adverse effects to alignment during subsequent photolithography processes (Peng ¶0023, 0037).
Regarding claim 12, Liu in view of Vogt and Huang teaches: The method of claim 1, wherein the forming the first gate dielectric layer (Liu 307) on the first region (Liu 302) of the semiconductor substrate (Liu 300) and the second gate dielectric layer (Liu 308) on the second region (Liu 301) of the semiconductor substrate comprises:
a) forming a first gate dielectric layer (Liu 307) on the semiconductor substrate (Liu 300)(Liu fig 4, ¶0062);
c) forming a second gate dielectric layer (Liu 308) in the second region of the semiconductor substrate (Liu fig 4, ¶0062); and
d) wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer (Liu fig 4, ¶0062).
Liu in view of Vogt and Huang does not teach: b) selectively removing the first gate dielectric layer on the second region and retaining the first gate dielectric layer on the first region.
Peng, in the same field of endeavor of semiconductor device manufacturing, teaches: a) forming a first gate dielectric layer (Peng 102, ¶0018, “oxide”) on a semiconductor substrate (Peng 101)(Peng fig 1A, ¶0018);
b) selectively removing the first gate dielectric layer on a second region (Peng “second region”, ¶0019, a region not including PR1, fig 1B) and retaining the first gate dielectric layer on a first region (“first region”, ¶0019, a region including PR1, fig 1B)(Peng fig 1B, ¶0019);
c) forming a second gate dielectric layer (Peng 103) in the second region of the semiconductor substrate (Peng fig 1C, ¶0019); and
d) wherein a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer (Peng ¶0021, “the thickness of oxide layer 103 is about 30 Å … thickness of oxide layer 102 may increase to about 70 Å”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to replace the formation steps of Liu in view of Vogt and Huang with that of Peng, and such that it includes “selectively removing the first gate dielectric layer on the second region and retaining the first gate dielectric layer on the first region”, in order to allow for an increased growth rate of the first gate dielectric layer during increased thickness (Peng ¶0020), thereby allowing an overall increase in the growth rate for the first gate dielectric layer and/or a decreased process time to form the first gate dielectric layer.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (CN 102184871 A, English translation of description provided in previous office action, as cited in IDS dated 08/25/2025, hereafter Liu) in view of Vogt et al (US 20150235864 A1, hereafter Vogt) and Huang et al (US 7521304 B1, hereafter Huang), as applied to claim 15 above, and further in view of Zhao et al (CN 109585376 A, English translation of description provided, hereafter Zhao).
Regarding claim 16, Liu in view of Vogt and Huang teaches: The method of claim 15, wherein the power device comprises a laterally-diffused metal-semiconductor field-effect transistor (Liu “LDMOS”, “power device”, ¶0003, 0069, 0079, fig 8, at least capable thereof; see MPEP 2112.01), and the high-density device comprises a metal-oxide-semiconductor field-effect transistor (Liu “CMOS”, fig 8, ¶0069, at least capable thereof; see MPEP 2112.01) used in one of logic circuits, microprocessors, and storage circuits.
Liu in view of Vogt and Huang does not explicitly teach: the high-density device used in one of logic circuits, microprocessors, and storage circuits.
Zhao, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a high-voltage device (Zhao “high-voltage devices”, ¶0005, 0094, similar to Liu “LDMOS”, fig 8) in a first region (Zhao 221, ¶0094, left side with respect to fig 17); and
forming a low-voltage device (Zhao “low-voltage devices”, ¶0005, 0094, similar to Liu “CMOS”, fig 8) in a second region (Zhao 222, ¶0094, right side with respect to fig 17);
wherein the high and low-voltage devices are used in power management circuits or storage circuits (Zhao ¶0005).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Liu in view of Vogt and Huang with the teaching of Zhao, such that “the high-density device used in one of logic circuits, microprocessors, and storage circuits”, in order to realize a power management and/or storage device on the same substrate, thereby improving integration of the device (Zhao ¶0005).
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argues at page 7:
Liu uses a mask for ion implantation, not as a stable mask for the etching of polysilicon, which enables the formation of a nanoscale second gate, and which allows the integration of nanoscale high-density devices and non-nanoscale power devices.
Examiner’s response:
The examiner respectfully disagrees. Liu explicitly teaches “etching the polysilicon layer and the silicon nitride layer by dry etching method”, where the silicon nitride layer forms a “hard mask” (Liu ¶0064). Liu’s barrier layer 310 serves a dual function: a hard mask for polysilicon gate etching, and implantation barrier during well formation (Liu ¶0066-0067).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen (US 20070200179 A1) is cited as an example of an analogous device further using amorphous carbon in semiconductor manufacturing.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818