DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (method of manufacturing a finfet device) claims 15-34 in the reply filed on 11/13/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15-18,21-25,28-31, and 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200343144 A1 Li et al hereafter “Li”.
Claim 15 Li teaches a manufacturing method of a semiconductor device (fig. 1), the semiconductor device comprising a substrate (290 fig. 5A-B), a plurality of fins (200 fig. 5A-5B) extending upward from the substrate, and a gate structure (350 and 340 fig. 5A-5B) covering the fins, the method manufacturing of the semiconductor device comprising:
forming a photoresist layer on the gate structure (comprising but not limited to 602 fig. 6A-6B, disclosed as including photoresist material Paragraph 0037 “the block mask 602 is deposited and an anti-reflecting material can be deposited on top. The (single) block mask 602 and anti-reflective material can be patterned into the desired shape with openings 604 and 606 by depositing a photoresist material (not shown) on top, exposing the photoresist material, etching the photoresist material along with the block mask layer and anti-reflective material underneath as desired, and removing the photoresist material. As a result, the (single) block mask 602 has been formed with openings 604 and 606 in preparation for the single diffusion break and double diffusion break, respectively”), developing and removing a part of the photoresist layer (sufficiently disclosed paragraph 0037), so that the photoresist layer is patterned to form an opening (604 fig. 6A) corresponding to a top (central top surface the fin fig. 6A) location of a first fin (200 of X1 fig. 6A) to be removed among the fins (sufficiently illustrated fig. 6A);
etching the first fin and the gate structure covering the first fin to form a recessed region (702 fig. 7A) in the gate structure (sufficiently illustrated fig. 7A); and
filling an insulating material (comprising 802 and 804 fig. 8A-B) into the recessed region.
Claim 16 Li teaches as shown above the manufacturing method according to claim 15, wherein the semiconductor device further comprises a source region and a drain region (404 source and drain epitaxial regions fig. 8A-8B) on opposite sides of the gate structure (sufficiently illustrated fig. 8A-B), and the fins pass through the source region and the drain region [sufficiently illustrated in by 202 of X1 and of X2 in fig. 8A-B in conjunction with FINS of fig. 1], and a number of remaining unetched fins of the fins in the gate structure is less than a number of the fins in the source region and the drain region [sufficiently illustrated fig. 1 in conjunction with fig. 8A-B, Note examiners interpretation under broadest reasonable interpretation, fig. 1 of Li illustrates 8 total fins that pass through the source and the drain region (sufficiently illustrated in conjunction cross sections X1 and X2 in figs. 8A-B) all of which under the interpretation that “a gate structure” refers to a collective gate structure, 0 fins remain unetched in the gate region to form fin cuts 152 and 150, Alternatively when interpreting “a gate structure” as a singular gate structure, 4 unetched fins remain in the singular gate structure comprising fun cut 150; in either case “a number of remaining unetched fins of the fins in the gate structure is less than a number of the fins in the source region and the drain region” [0 out of 8 or 4 out of 8]. In view of this the examiner recommended (although not required) further defining claimed limitations as it is unclear to the examiner how this limitation would not occur wherein fins pass through source and drain regions and at least one fin is etched in a gate region].
Claim 17 Li teaches as shown above the manufacturing method according to claim 15, further comprising:
developing and removing another part of the photoresist layer (sufficiently disclosed Paragraph 0037 “the block mask 602 is deposited and an anti-reflecting material can be deposited on top. The (single) block mask 602 and anti-reflective material can be patterned into the desired shape with openings 604 and 606 by depositing a photoresist material (not shown) on top, exposing the photoresist material, etching the photoresist material along with the block mask layer and anti-reflective material underneath as desired, and removing the photoresist material. As a result, the (single) block mask 602 has been formed with openings 604 and 606 in preparation for the single diffusion break and double diffusion break, respectively”), so that the photoresist layer is patterned to form another opening (606 fig. 6B) corresponding to a top location of a second fin (200 of X2 fig. 6B) to be partially etched among the fins (sufficiently illustrated fig. 7B under broadest reasonable interpretation only part of the fin is etched);
etching a portion of the second fin and the gate structure covering the second fin to form another recessed region (704 fig. 7B) in the gate structure; and
filling the insulating material into the another recessed area region [sufficiently illustrated fig. 8B].
Claim 18 Li teaches as shown above the manufacturing method according to claim 17, wherein a height of the second fin is less than a height of the remaining unetched fins [met under broadest reasonable interpretation in view of fig. 1 and fig. 9A-B regarding the structure of the fins, see annotation below, note the examiner has interpreted that a second fin may be a collective second fin and/or comprises sub-fins].
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Annotated fig. 9B: highlighting a height of the second fin and a height of the remaining unetched fins
Claim 21 Li teaches a manufacturing method of a semiconductor device (fig. 1), comprising:
forming a source region (a source region is sufficiently met by 404 fig. 5A-B, see annotation below), a drain region ( a drain region is sufficiently met by 404 fig. 5A-B, see annotation below) and a plurality of fins (200 fig. 4A-B and FINS fig. 1) on a substrate (290 fig. 4A-B), the fins extending upward from the substrate and passing through the source region and the drain region [sufficiently illustrated fig. 5A-B];
forming a channel region [sufficiently illustrated fig. 5A-B, see annotation below] within the fins and located between the source region and the drain region [sufficiently illustrated fig. 5A-B]; and
etching at least one of the fins (200 of X1 fig. 7A) to form a reduced number of the fins in the channel region [sufficiently illustrated fig. 7A-B, in conjunction with fig. 199].
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Annotated fig. 5A: highlighting a source region, a drain region, and a channel region
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Annotated fig 5A: highlighting a source region, a drain region, and a channel region in view of cross sections X1, X2, and X3
Claim 22 Li teaches as shown above the manufacturing method according to claim 21, further comprising forming a gate structure (250 and 240 fig. 5A-5B and “gates” fig. 1) located on the fins and the channel region, and the source region and the drain region are located on opposite sides of the gate structure [sufficiently illustrated fig. 5A-5B].
Claim 23 Li teaches as shown above the manufacturing method according to claim 22, wherein a number of remaining unetched fins in the gate structure is less than a number of the fins located in the source region and the drain region [sufficiently illustrated fig. 1 in conjunction with fig. 7A, Note it is unclear to the examiner how this limitation would not occur wherein fins pass through source and drain regions and at least one fin is etched in a gate region, the etch of recess 702 mathematically reduces the number of remaining unetched fins in the gate structure to be at least 1 less than the number of fins located in the source region and the drain region].
Claim 24 Li teaches as shown above the manufacturing method according to claim 23, further comprising etching another one of the fins (200 of X2 fig. 7B) to form a partially etched fin [only part of 200 of X2 is etched fig. 7B] among the remaining unetched fins [met under broadest reasonable interpretation fig. 6B illustrates it as one of the remaining unetched fin, fig. 7B illustrates as an etched fin, note the language of the claims does not explicitly reference or claim the sequence of operations or at which point in time the fin exists as one of the remaining unetched fin and limitations from the specification have not been imported into the claims ].
Claim 25 Li teaches as shown above the manufacturing method according to claim 24, wherein a height of the partially etched fin is less than a height of the remaining unetched fins. [met under broadest reasonable interpretation in view of fig. 1 and fig. 9A-B regarding the structure of the fins, see annotation below, note the examiner has interpreted that a partially etched fin may be a collective fin and/or comprises sub-fins]
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Annotated fig. 9B: highlighting a height of the partially etched fin and a height of the remaining unetched fins
Claim 28 Li teaches A manufacturing method of a semiconductor device (fig. 1), comprising:
forming a plurality of fins (200 fig. 5A-B) on a substrate (290 fig. 5A-B), the fins extending upward from the substrate and passing through a source region (comprising a portion of 290 contacting 404 fig. 5A, see annotation below) and a drain region (comprising a laterally adjacent portion of 290 contacting 404 fig. 5A, see annotation below) of the substrate;
forming a channel region (see annotation below) within the fins and located between the source region and the drain region;
forming a gate structure (340 and 350 fig. 5A-B and/or “gate” fig. 1) covering the fins and the channel region [sufficiently illustrated fig. 5A-B]; and
form a recessed region (702 fig. 7A) in the gate structure corresponding to a top location of a first fin (200 of X1 fig. 7A) to be removed among the fins and etching the first fin to form a reduced number of the fins in the channel region [sufficiently illustrated fig. 6A to 7A reduced from 3 to 2 within the X1 cross-section].
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Annotated fig. 5A: highlighting a source region, a drain region, and a channel region
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Annotated fig 5A: highlighting a source region, a drain region, and a channel region in view of cross sections X1, X2, and X3
Claim 29 Li teaches as shown above the manufacturing method according to claim 28, wherein a number of remaining unetched fins in the gate structure is less than a number of the fins located in the source region and the drain region [sufficiently illustrated fig. 1 in conjunction with fig. 7A, Note it is unclear to the examiner how this limitation would not occur wherein fins pass through source and drain regions and at least one fin is etched in a gate region, the etch of recess 702 mathematically reduces the number of remaining unetched fins in the gate structure to be at least 1 less than the number of fins located in the source region and the drain region].
Claim 30 Li teaches as shown above the manufacturing method according to claim 29, further comprising form another recessed region (704 fig. 7B) in the gate structure and etching a second fin (200 of X2 fig. 7B) of the fins to form a partially etched fin among the remaining unetched fins [met under broadest reasonable interpretation fig. 6B illustrates it as one of the remaining unetched fin, fig. 7B illustrates as an etched fin, note the language of the claims does not explicitly reference or claim the sequence of operations or at which point in time the fin exists as one of the remaining unetched fin and limitations from the specification have not been imported into the claims ].
Claim 31 Li teaches as shown above the manufacturing method according to claim 30, wherein a height of the partially etched fin is less than a height of the remaining unetched fins [sufficiently illustrated fig. 9B].
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Annotated fig. 9B: highlighting a height of the partially etched fin and a height of the remaining unetched fins
Claim 34 Li teaches as shown above the manufacturing method according to claim 28, further comprising filling an insulating material (comprising 802 and 804 fig. 9A-B) into the recessed region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20, 26-27, and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Li as applied to the claims above, and further in view of US 20230197826 A1 Radlinger et al hereafter “Radlinger”.
Claim 19 Li teaches as shown above the manufacturing method according to claim 15, further comprising:
Li does not teach forming an interlayer dielectric layer on the gate structure;
forming a first conductive metal and a second conductive metal in the interlayer dielectric layer; and
forming a metal layer on the first conductive metal, the second conductive metal and the interlayer dielectric layer, wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively.
Radlinger teaches forming an interlayer dielectric layer (714 fig. 7A) on a gate structure (comprising 708 fig. 7A);
forming a first conductive metal (sufficiently illustrated fig. 7A comprising a first portion of 716, see annotation below) and a second conductive metal (sufficiently illustrated fig. 7A comprising a second portion of 716, see annotation below) in the interlayer dielectric layer; and
forming a metal layer (sufficiently illustrated fig. 7A comprising a third portion of 716, see annotation below) on the first conductive metal, the second conductive metal and the interlayer dielectric layer (sufficiently illustrated fig. 7A), wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively (sufficiently illustrated fig. 7A).
It would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li in view of Radlinger such that “forming an interlayer dielectric layer on the gate structure; forming a first conductive metal and a second conductive metal in the interlayer dielectric layer; and forming a metal layer on the first conductive metal, the second conductive metal and the interlayer dielectric layer, wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively” occurs to enable electrical coupling of across segments/stacks of the gate structure [“A local conductive interconnect 716 electrically couples the exposed top surface of the metal gate electrode of adjacent gate stacks 708 and extends over an intervening SAGE wall (middle 710)” Paragraph 0075 Radlinger]
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Radlinger Annotated fig. 7A: highlighting a first conductive metal a second conductive metal, and a metal layer
Claim 20 Li in view of Radlinger teaches as shown above the manufacturing method according to claim 19, wherein the semiconductor device comprises a first semiconductor device (right transistor fig. 9B sufficiently illustrated not labeled, see annotation below) and a second semiconductor device (left transistor fig. 9B sufficiently illustrated not labeled, see annotation below), the gate structure of the first semiconductor device and the gate structure of the second semiconductor device share the metal layer (met in view of the modification of Radlinger, illustrated Radlinger fig. 7A), and a number of remaining unetched fins of the fins [under broadest reasonable interpretation illustrated as 2 remaining unetched fins of the fins within the cross section of X2 fig. 9B] in the first semiconductor device and a number of remaining unetched fins of the fins [under broadest reasonable interpretation illustrated as 1 remaining unetched fins of the fins within the cross section of X2 fig. 9B ] in the second semiconductor device are not equal (sufficiently illustrated fig. 9B). [examiner notes: the “first semiconductor device” and the “second semiconductor device” appear to have a very broad general meaning and the context of the claims do not further limit what can be considered the first semiconductor device and the second semiconductor device. This leads to a plurality of equally valid interpretations of the claims that maybe applied to the prior art that would overcome the language of the claims under broadest reasonable interpretation, for the sake of brevity the examiner only applied one such interpretation within this action. The examiner recommends (although not required) amending to narrow the scope and/or better defining what the semiconductor devices are within the context of the claims.]
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Li Annotated fig. 9B: highlighting a first semiconductor device and a second semiconductor device
Claim 26 Li teaches as shown above the manufacturing method according to claim 22, further comprising:
Li does not teach forming an interlayer dielectric layer on the gate structure;
forming a first conductive metal and a second conductive metal in the interlayer dielectric layer; and
forming a metal layer on the first conductive metal, the second conductive metal and the interlayer dielectric layer, wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively.
Radlinger teaches forming an interlayer dielectric layer (714 fig. 7A) on a gate structure (comprising 708 fig. 7A);
forming a first conductive metal (sufficiently illustrated fig. 7A comprising a first portion of 716, see annotation below) and a second conductive metal (sufficiently illustrated fig. 7A comprising a second portion of 716, see annotation below) in the interlayer dielectric layer; and
forming a metal layer (sufficiently illustrated fig. 7A comprising a third portion of 716, see annotation below) on the first conductive metal, the second conductive metal and the interlayer dielectric layer (sufficiently illustrated fig. 7A), wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively (sufficiently illustrated fig. 7A).
It would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li in view of Radlinger such that “forming an interlayer dielectric layer on the gate structure; forming a first conductive metal and a second conductive metal in the interlayer dielectric layer; and forming a metal layer on the first conductive metal, the second conductive metal and the interlayer dielectric layer, wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively” occurs to enable electrical coupling of across segments/stacks of the gate structure [“A local conductive interconnect 716 electrically couples the exposed top surface of the metal gate electrode of adjacent gate stacks 708 and extends over an intervening SAGE wall (middle 710)” Paragraph 0075 Radlinger]
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Radlinger Annotated fig. 7A: highlighting a first conductive metal a second conductive metal, and a metal layer
Claim 27 Li in view of Radlinger teaches as shown above the manufacturing method according to claim 26, wherein the semiconductor device comprises a first semiconductor device (a right portion of fig. 9B) and a second semiconductor device (a left portion of fig. 9B), the gate structure of the first semiconductor device and the gate structure of the second semiconductor device share the metal layer (met in view Radlinger fig. 7A and the modification made above), and a number of remaining unetched fins of the fins in the first semiconductor device (2 illustrated fig. 9B) and a number of remaining unetched fins of the fins in the second semiconductor device (1 fig. 9B) are not equal (sufficiently illustrated fig. 9B).
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Li Annotated fig. 9B: highlighting a first semiconductor device and a second semiconductor device
Claim 32 Li teaches the manufacturing method according to claim 28, further comprising:
Li does not teach forming an interlayer dielectric layer on the gate structure;
forming a first conductive metal and a second conductive metal in the interlayer dielectric layer; and
forming a metal layer on the first conductive metal, the second conductive metal and the interlayer dielectric layer, wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively.
Radlinger teaches forming an interlayer dielectric layer (714 fig. 7A) on a gate structure (comprising 708 fig. 7A);
forming a first conductive metal (sufficiently illustrated fig. 7A comprising a first portion of 716, see annotation below) and a second conductive metal (sufficiently illustrated fig. 7A comprising a second portion of 716, see annotation below) in the interlayer dielectric layer; and
forming a metal layer (sufficiently illustrated fig. 7A comprising a third portion of 716, see annotation below) on the first conductive metal, the second conductive metal and the interlayer dielectric layer (sufficiently illustrated fig. 7A), wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively (sufficiently illustrated fig. 7A).
It would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li in view of Radlinger such that “forming an interlayer dielectric layer on the gate structure; forming a first conductive metal and a second conductive metal in the interlayer dielectric layer; and forming a metal layer on the first conductive metal, the second conductive metal and the interlayer dielectric layer, wherein the metal layer is electrically connected to the gate structure through the first conductive metal and the second conductive metal respectively” occurs to enable electrical coupling of across segments/stacks of the gate structure [“A local conductive interconnect 716 electrically couples the exposed top surface of the metal gate electrode of adjacent gate stacks 708 and extends over an intervening SAGE wall (middle 710)” Paragraph 0075 Radlinger]
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Radlinger Annotated fig. 7A: highlighting a first conductive metal a second conductive metal, and a metal layer
Claim 33 Li in view of Radlinger teaches the manufacturing method according to claim 32, wherein the semiconductor device comprises a first semiconductor device (a right portion of fig. 9B) and a second semiconductor device (a left portion of fig. 9B), the gate structure of the first semiconductor device and the gate structure of the second semiconductor device share the metal layer (met in view of the modification of Radlinger fig. 7A as shown above, ), and a number of remaining unetched fins of the fins in the first semiconductor device (2 illustrated fig 9B) and a number of remaining unetched fins of the fins in the second semiconductor device (1 illustrated fig. 9B) are not equal (sufficiently illustrated fig. 9B).
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Li Annotated fig. 9B: highlighting a first semiconductor device and a second semiconductor device
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893