DETAILED ACTION
This Office action is in response to the amendment filed 8 June 2026. By this amendment, claims 9, 12, 14, and 19 are amended. Claims 1-19 are currently pending; claims 2 and 13 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8 June 2026 have been fully considered but they are not persuasive; the rejections of the claims have been modified in response to Applicant's amendments to the claims. The amended limitations (and Applicant’s arguments regarding the amended limitations) are addressed by the modified rejections below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0373341 A1 to Jo et al. (hereinafter “Jo”) in view of JP 2003-175500 to Yamaguchi et al. (citations refer to the English machine translation attached to the previous Office action mailed 9 April 2026; hereinafter “Yamaguchi”).
Regarding independent claim 9, Jo (Figs. 1, 8) discloses a sensor package structure, comprising:
a substrate 300 (¶ 0026);
a sensor chip 100 (¶ 0025) disposed on the substrate along a predetermined direction (parallel with top surface of substrate) and electrically coupled to the substrate (Fig. 1), wherein a top surface of the sensor chip has a sensing region 110 (¶ 0020) and a carrying region (¶ 0020 - “non-sensing region”) that surrounds the sensing region;
an adhesive layer 200 (¶ 0019) having a ring shape and being disposed on the carrying region of the sensor chip (Figs. 1, 8), wherein the adhesive layer has an inner side (facing 110) and an outer side (facing 320) that is opposite to the inner side and that is spaced apart from the inner side by a predetermined width along a width direction perpendicular to the predetermined direction, and wherein, in a cross-sectional view of the adhesive layer perpendicular to the predetermined direction, a minimum width of the adhesive layer in the width direction is greater than or equal to 50% of the predetermined width (Fig. 8);
a light-permeable layer 400 (¶ 0019) having an outer surface (top) and an inner surface (bottom) that is opposite to the outer surface, wherein the light-permeable layer is disposed on the adhesive layer 200, and the inner surface of the light-permeable layer, the inner side of the adhesive layer, and the sensor chip 100 jointly define an enclosed space (Fig. 1); and
an encapsulant 320 (¶ 0037) formed on the substrate 300, wherein the sensor chip 100, the adhesive layer 200, and the light-permeable layer 400 are embedded in the encapsulant 320, and the outer surface of the light-permeable layer 400 is at least partially exposed from the encapsulant 320 (Fig. 1);
wherein the adhesive layer 200 has at least one buffering cavity (120b disposed therein; ¶ 0075) that is arranged therein and that is spaced apart from the inner side and the outer side thereof (Fig. 8).
Jo fails to expressly disclose: wherein the adhesive layer has a plurality of wave-shaped slots respectively recessed in the inner side and the outer side thereof and penetrating therethrough along the predetermined direction, wherein any two of the wave-shaped slots located adjacent to each other and respectively arranged on the inner side and the outer side are only partially overlapped with each other along the width direction.
In the same field of endeavor, Yamaguchi (Figs. 1, 4d) discloses a sensor package structure including an adhesive layer 7 (p. 4, para. 6), wherein the adhesive layer has a plurality of wave-shaped slots (Fig. 4d) respectively recessed in the inner side (right side) and the outer side (left side) thereof and penetrating therethrough along the predetermined direction (parallel with the top surface of the substrate), wherein any two of the wave-shaped slots located adjacent to each other and respectively arranged on the inner side and the outer side are only partially overlapped with each other along the width direction (Fig. 4d). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the adhesive of Jo to provide the pattern as disclosed by Yamaguchi for the purpose of reducing the stress between adjoining layers (p. 3, ¶ 0011).
Regarding claim 10, Jo and Yamaguchi disclose the sensor package structure according to claim 9, Yamaguchi (Fig. 4d) discloses wherein, in any two of the M number of the wave-shaped slots located adjacent to each other and respectively arranged on the inner side and the outer side, a wave crest of one of the two wave-shaped slots corresponds in position to a wave trough of another one of the two wave-shaped slots along the width direction (Yamaguchi, Fig. 4d).
Regarding claim 11, Jo and Yamaguchi disclose the sensor package structure according to claim 9, Yamaguchi (Figs. 1, 4d) discloses wherein the adhesive layer 7 includes a plurality of segments sequentially connected to form the ring shape (see Fig. 1b), and wherein the wave-shaped slots are formed on at least one of the segments (Fig. 4d - illustrating other pattern for forming adhesive 7; p. 4, para. 4).
Regarding claim 12, Jo and Yamaguchi disclose the sensor package structure according to claim 9, Jo (Fig. 8) teaches further wherein the at least one buffering cavity (120b disposed therein) penetrates adhesive layer 200 along the predetermined direction (Fig. 8).
Regarding independent claim 14, Jo (Figs. 1, 8) discloses a sensor package structure, comprising:
a substrate 300 (¶ 0026);
a sensor chip 100 (¶ 0025) disposed on the substrate along a predetermined direction (parallel with top surface of substrate) and electrically coupled to the substrate (Fig. 1), wherein a top surface of the sensor chip has a sensing region 110 (¶ 0020) and a carrying region (¶ 0020 - “non-sensing region”) that surrounds the sensing region;
an adhesive layer 200 (¶ 0019) having a ring shape and being disposed on the carrying region of the sensor chip (Figs. 1, 8), wherein the adhesive layer has an inner side (facing 110) and an outer side (facing 320) that is opposite to the inner side and that is spaced apart from the inner side by a predetermined width along a width direction perpendicular to the predetermined direction, and wherein, in a cross-sectional view of the adhesive layer perpendicular to the predetermined direction, a minimum width of the adhesive layer in the width direction is greater than or equal to 50% of the predetermined width (Fig. 8);
a light-permeable layer 400 (¶ 0019) having an outer surface (top) and an inner surface (bottom) that is opposite to the outer surface, wherein the light-permeable layer is disposed on the adhesive layer 200, and the inner surface of the light-permeable layer, the inner side of the adhesive layer, and the sensor chip 100 jointly define an enclosed space (Fig. 1); and
an encapsulant 320 (¶ 0037) formed on the substrate 300, wherein the sensor chip 100, the adhesive layer 200, and the light-permeable layer 400 are embedded in the encapsulant 320, and the outer surface of the light-permeable layer 400 is at least partially exposed from the encapsulant 320 (Fig. 1);
wherein the adhesive layer 200 has at least one buffering cavity (120b disposed therein; ¶ 0075) that is arranged therein and that is spaced apart from the inner side and the outer side thereof (Fig. 8).
Jo fails to expressly disclose wherein the adhesive layer has a plurality of rectangular slots respectively recessed in the inner side and the outer side thereof and penetrating therethrough along the predetermined direction, wherein any two of the rectangular slots located adjacent to each other and respectively arranged on the inner side and the outer side are not overlapped with each other along the width direction.
In the same field of endeavor, Yamaguchi (Figs. 1, 2) discloses a sensor package structure including an adhesive layer 7 (p. 4, para. 6), wherein the adhesive layer has a plurality of rectangular slots (Fig. 1b, 2) respectively recessed in the inner side (right side) and the outer side (left side) thereof and penetrating therethrough along the predetermined direction (parallel with the top surface of the substrate), wherein any two of the rectangular slots located adjacent to each other and respectively arranged on the inner side and the outer side are not overlapped with each other along the width direction (Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the adhesive of Jo to provide the pattern as disclosed by Yamaguchi for the purpose of reducing the stress between adjoining layers (p. 3, ¶ 0011).
Regarding claim 15, Jo and Yamaguchi disclose the sensor package structure according to claim 14, Yamaguchi (Fig. 2) discloses further wherein any one of the rectangular slots has a slot opening arranged on the inner side or the outer side of the adhesive layer 7 and having a slot width, and wherein any two of the rectangular slots located adjacent to each other and respectively arranged on the inner side and the outer side of the adhesive layer have a distance therebetween that is greater than or equal to the slot width (Fig. 2).
Regarding claim 16, Jo and Yamaguchi disclose the sensor package structure according to claim 14, wherein any one of the rectangular slots has a slot opening arranged on the inner side or the outer side of the adhesive layer and having a slot width (Yamaguchi, Fig. 2).
Jo and Yamaguchi fail to expressly disclose wherein any two of the rectangular slots located adjacent to each other and both arranged on the inner side or the outer side have a distance therebetween that is at least three times of the slot width. Nonetheless, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, the following limitations are considered mere dimensional limitations: “wherein any two of the rectangular slots located adjacent to each other and both arranged on the inner side or the outer side have a distance therebetween that is at least three times of the slot width.” The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitations, and thus are found to be prima facie obvious.
Regarding claim 17, Jo and Yamaguchi disclose the sensor package structure according to claim 14, Yamaguchi (Figs. 1, 2) discloses wherein the adhesive layer 7 includes a plurality of segments sequentially connected to form the ring shape, and wherein the rectangular slots are formed on at least one of the segments (Figs. 1b, 2).
Regarding claim 18, Jo and Yamaguchi disclose the sensor package structure according to claim 17, Yamaguchi (Figs. 1, 2) discloses wherein any one of the rectangular slots has a slot opening arranged on the inner side or the outer side of the adhesive layer 7 and a slot bottom that is arranged away from the slot opening, and wherein, in any two of the rectangular slots formed on a same one of the segments and respectively arranged on the inner side and the outer side, the slot bottoms are coplanar with each other (Fig. 2).
Regarding claim 19, Jo and Yamaguchi disclose the sensor package structure according to claim 14, Jo (Fig. 8) discloses wherein the at least one buffering cavity (120b disposed therein) penetrates adhesive layer 200 along the predetermined direction (Fig. 8).
Allowable Subject Matter
Claims 1 and 3-8 are allowed for the reasons as set forth in the Non-Final Rejection mailed 9 April 2026.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
8 August 2026
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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