DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 11/05/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 20-27, 29-37 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US Publication No. 2022/0271130) in view of Chen et al (US Publication No. 2021/0098468).
Regarding claim 18, Su discloses a method for forming a semiconductor device structure, comprising: providing first and second source/drain features on opposing sides of a gate structure Fig 2, Fig 3 and Fig 15; forming a first interlayer dielectric (ILD) Fig 2, 214 over the first and second source/drain features¶0018; removing portions of the first ILD to form first and second contact openings¶0018-0019 Fig 3, wherein the first contact opening is extended to expose portions of the first source/drain feature and the gate structure¶0018, and the second contact opening is extended to expose a portion of the second source/drain feature¶0018 Fig 2 and Fig 3; filling the first and second contact openings with a conductive material to form first and second conductive features Fig 3, 222, respectively; performing a planarization process so that top surfaces of the gate structure, the first conductive feature, and the second conductive feature are substantially co-planar ¶0020 Fig 3;forming a second ILD Fig 4, 228 over the first ILD Fig 4; removing portions of the second ILD to form a butted contact opening exposing the top surfaces of the first conductive feature and the gate structure Fig 5; and filling the butted contact opening with one or more conductive materials to form a butted contact Fig 6.
Su discloses all the limitations except the shape of the opening.
Whereas Chen discloses forming conductive features in the L-shaped profile Fig 3.
Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Additionally, it would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 20, Su discloses removing portions of the second ILD to form a via contact opening exposing the top surface of the second conductive feature; and filling the via contact opening with a third conductive material Fig 9 and Fig 10.
Regarding claim 21, Su discloses a method of forming a semiconductor device structure, comprising: forming a plurality of gate structures over a substrate Fig 3 and Fig 15 ;forming a first contact etch stop layer Fig 2, 212 ¶0018 and a first interlayer dielectric Fig 2, 214¶0018 over the substrate and the gate structures; forming contact openings through the first interlayer dielectric and the first contact etch stop layer to expose source/drain features Fig 3 ¶0020;filling the contact openings with a conductive material Fig 3, 222 ¶0020 to form conductive features; forming a third interlayer dielectric Fig 4, 228 over the conductive features and the gate structures Fig 4;etching the third interlayer dielectric Fig 4, 228 to form butted contact openings Fig 5 that concurrently expose a top surface of at least one conductive feature; and forming a butted contact in the butted contact opening to electrically connect the conductive feature with the gate electrode Fig 6 and Fig 10.
Su discloses all the limitations except for having the contact opening expose the top surface of the gate electrode.
Whereas Chen discloses etching the interlayer dielectric Fig 11 to form butted contact openings Fig 11 that expose a top surface of a gate electrode; and forming a butted contact in the butted contact opening to electrically connect the source feature with the gate electrode Fig 13.
Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Regarding claim 22, Su discloses wherein forming the butted contact comprises depositing a metal selected from W, Co, AI, Ru, or Cu ¶0023.
Regarding claim 23, Chen discloses wherein forming the contact openings comprises patterning the first interlayer dielectric to define an L-shaped contact profile Fig 3. Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Additionally, it would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 24, Su discloses: forming a silicide layer Fig 13, 218 between the conductive feature and the epitaxial source/drain feature.
Regarding claim 25, Su discloses wherein the butted contact and the conductive feature have coplanar upper surfaces Fig 13.
Regarding claim 26, Chen discloses wherein the butted contact extends across a source/drain region of a first transistor and a gate region of a second transistor Fig 3. Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Regarding claim 27, Su discloses wherein the contact openings have a first width (W1) at a top portion and a smaller width (W2) at a bottom portion, and W1:W2 is about 1.5:1 to 3:1 Fig 13.
Regarding claim 29, Su discloses method of manufacturing a semiconductor device structure Fig 15, comprising: forming a plurality of transistors each having a gate structure and a source/drain feature Fig 15;forming a first dielectric stack Fig 2, 212/214 comprising a contact etch-stop layer Fig 2, 212 and a first interlayer dielectric Fig 2, 214 over the transistors¶0018; etching the first dielectric stack to form openings exposing portions of the source/drain features and a gate dielectric ¶0020;forming conductive features in the openings such that each conductive feature comprises a first portion adjacent the gate structure and a second portion overlying the source/drain feature Fig 3;planarizing the conductive features and the first dielectric stack until top surfaces of the conductive features and gate electrodes are coplanar ¶0020;forming a second dielectric stack over the planarized structure Fig 4;etching the second dielectric stack to form butted-contact openings exposing both the top surfaces of the conductive features and the top surfaces of the gate Fig 5;and filling the butted-contact openings with a conductive material to form butted contacts electrically coupling the conductive features and the gate electrodes Fig 6.
Su discloses all the limitations except for having the contact opening expose the top surface of the gate electrode and the shape of the opening.
Whereas Chen discloses etching the interlayer dielectric Fig 11 to form butted contact openings Fig 11 that expose a top surface of a gate electrode; and forming a butted contact in the butted contact opening to electrically connect the source feature with the gate electrode Fig 13 and forming conductive features in the L-shaped openings Fig 3.
Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 30, Su discloses wherein the conductive material of the butted contacts comprises W, Co, TiN, TaN, or a Ru-Co alloy ¶0023.
Regarding claim 31, Chen discloses wherein the first portion (153a) of each L-shaped opening has a first width (W3) and the second portion of each L-shaped opening has a second width (W4), and W3:W4 has a ratio of about 1.5:1 to 3:1 Fig 3 and Fig 13. Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Additionally, it would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 32, Su discloses: forming a silicide interface Fig 13, 218
between each conductive feature and its corresponding source/drain feature.
Regarding claim 33, Chen discloses wherein a portion of the conductive feature laterally contacts the gate dielectric Fig 13. Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Regarding claim 34, Su discloses wherein forming the butted contacts and via contacts comprises performing a same metallization process followed by chemical- mechanical polishing ¶0022-0023 and 0027.
Regarding claim 35, Su discloses wherein the butted contact overlaps both a gate electrode and a source/drain contact within a single lithography pattern Fig 6 and Fig 10.
Regarding claim 36, Chen discloses wherein the butted contacts and the conductive features reduce parasitic capacitance between the source/drain regions and the gate electrodes ¶0041-0042, 0068. Su and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact opening and incorporate the teachings of Chen to improve connectivity.
Regarding claim 37, Su discloses: forming an interconnect structure comprising inter-metal dielectric layers and conductive vias overlying the butted contacts Fig 13 and Fig 14.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US Publication No. 2022/0271130) in view of Chen et al (US Publication No. 2021/0098468) and in further view of Adetutu et al (US Publication No. 2011/0294292).
Regarding claim 19, Su discloses all the limitations but silent on having a second conductive material. Whereas Adetutu discloses wherein the butted contact is formed by filling a first half of the butted contact opening with a first conductive material and filling a second half of the butted contact opening with a second conductive material Fig 14. Su and Adetutu are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact material and incorporate the teachings of Adetutu since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US Publication No. 2022/0271130) in view of Chen et al (US Publication No. 2021/0098468) in further view of Wang et al (US Publication No. 2023/0121210).
Regarding claim 28, Su discloses all the limitations but silent on having contact arrangement. Whereas Wang discloses wherein the butted contact and a via contact are formed to a same height above the third interlayer dielectric Fig 21B and Fig 22B.
Su and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Su because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the contact arrangement and incorporate the teachings of Wang as an alternative arrangement for ease in processing.
Conclusion
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811