DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, Modification I, in the reply filed on 2/6/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimura US 20160163806 A1 (hereinafter referred to as Nishimura).
Regarding claim 1, Nishimura teaches
A package structure, comprising:
a substrate (“drain layer 12” is formed from “n-type semiconductor substrate”, then thinned and doped, para. 0086 FIG. 1);
a conductive pad (“electrode layer 1, 1a” para. 0022 FIG. 1 and 4A-4B) disposed over the substrate; and
a conductive wire (“wire 2” para. 0022) comprising an end portion connected to the conductive pad (portion of “wire 2” connected to “electrode layer 1a”), wherein a grain arrangement of the end portion is distinct from a grain arrangement of the conductive pad (“electrode layer 1a” has a plurality of “grains 51.sub.j−2, 51.sub.j−1, 51.sub.j, 51.sub.j+1, 51.sub.j+2” have diameters similar to a thickness of “electrode layer 1a” while “grains 30” of “wire 2” are larger, para. 0046 and 0063 FIG. 3).
Regarding claim 5, Nishimura teaches the package structure as claimed in claim 1, wherein the end portion comprises a first grain (“grain 30” labeled in annotated FIG. 3), the conductive pad comprises a second grain and a third grain (“Grains 51” labeled in annotated FIG. 3), and the first grain is at least partially between the second grain and the third grain (As shown in annotated FIG. 3, some “grains 51.sub.j−2, 51.sub.j−1, etc.” are shown as being disposed at opposite ends of a first “grain 30” along the bonding direction and a portion of “grain 30” is below top portions of the second and third “grains 51” in annotated FIG. 3.)
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Regarding claim 8, Nishimura the package structure as claimed in claim 1, wherein a size of a grain of the end portion is greater than a size of a grain of the conductive pad (“grains 30” of “wire 2” are larger than “grains 51.sub.j−2, 51.sub.j−1, 51.sub.j, 51.sub.j+1, 51.sub.j+2”, para. 0063 FIG. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park.
Regarding 6, Nishimura the package structure as claimed in claim 5 but fails to expressly teach wherein the first grain contacts a crystallographic plane of the second grain and a crystallographic plane of the third grain.
Nevertheless, the examiner understands that “grains 51” include crystal planes because they are referred to as grains. The “grains 51” have different shapes, such that it is expected that the top surfaces have a crystallographic plane, regardless if “grain 51” is polycrystalline or single crystal. The first “grain 30” in annotated FIG. 3 above contacts the second “grain 51” and third “grain 51”. As such, it is understood that “grain 30” contacts a plane in each “grain 51”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the first grain “grain 30” contacts a crystallographic plane in each “grain 51” it contacts.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first grain in the end portion contacts crystallographic planes in the conductive pad. The metal of the conductive pad has grain structures and grain structures contain crystallographic planes.
Regarding claim 7, Nishimura teaches the package structure as claimed in claim 6 but fails to expressly teach wherein the end portion further comprises a fourth grain adjacent to the first grain, and a gap between the first grain and the fourth grain is greater than a gap between the second grain and the third grain.
Nevertheless, the “grains 30” are of a greater size than the “grains 51 (para. 0063). This implies that the boundaries or gaps between adjacent “grains 30” may be larger than the boundaries between “grains 51”. As suggested in annotated FIG. 3, the first “grain 30” has adjacent “grains 30” that have boundaries that are longer than the boundary between second and third “grains 51”. Furthermore, the gaps between “grains 51” are preferred to remain smaller so that movable ions do not move as easily through to the gate insulating films of the device and cause deterioration of the device (para. 0045). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the boundary between “grains 30” may be larger than the boundaries between “grains 51” because the “grains 30” are larger and have a greater surface area, such that the boundary with an adjacent “grain 30” may be larger. Smaller gaps between “grains 51” are desired so that gates of the semiconductor device are not deteriorated by the intrusion of ions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gap between the first and fourth grain is greater than the gap between the second and third grain. The grains of the end portion are larger and therefore adjacent grains may share a larger boundary. Smaller gaps in the conductive pad lead to a device with improved reliability over time.
Regarding claim 10, Nishimura teaches package structure as claimed in claim 1 but fails to expressly teach wherein the conductive pad comprises a first grain including a first upstanding portion proximal to the substrate and a first bending portion proximal to the end portion, and the first bending portion is more inclined than the first upstanding portion with respect to the substrate in a cross-sectional view.
Nevertheless, Nishimura teaches “grains 51” with diameters near to the thickness of “electrode layer 1a” so that damage due to the wirebonding process is minimized (para. 0043). Some of these “grains 51” have portions that bend in lateral directions as seen in FIG. 3 but they all appear to have different shapes. The differences in shape are understood to be due to process flows in the formation of “electrode layer 1a”. Even in cases where the grains are highly oriented, such as in a nanotwinned structure copper taught by Banik, cross sections show differences in shapes among different grains and along the same grain (see FIG. 1, 6A and 6B). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “grains 51” may have different shapes as long as the diameter is near or greater than the thickness of the “electrode layer 1a” so that cracking is prevented.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the grain may have different shapes, including an upstanding portion and a bent portion, so long as the size is similar to the thickness of the pad layer. Such a size helps prevent damage to the conductive pad during the wirebonding process.
Furthermore, changes in shape are held to be obvious over the prior art absent any persuasive evidence that the particular configuration of the claimed shape was significant (see MPEP 2144.4 Section B). The specification fails to disclose how the claimed shape affects the performance of semiconductor device.
Regarding claim 11, Nishimura teaches the package structure as claimed in claim 10 but fails to expressly teach wherein the conductive pad further comprises a second grain adjacent to the first grain, the second grain comprises a second upstanding portion and a second bending portion over the second upstanding portion, and the second bending portion is less inclined than the first bending portion with respect to the substrate in the cross-sectional view.
Nevertheless, Nishimura teaches “grains 51” with diameters near to the thickness of “electrode layer 1a” so that damage due to the wirebonding process is minimized (para. 0043). Some of these “grains 51” have portions that bend in lateral directions as seen in FIG. 3 but they all appear to have different shapes. The differences in shape are understood to be due to process flows in the formation of “electrode layer 1a”. Even in cases where the grains are highly oriented, such as in a nanotwinned structure copper taught by Banik, cross sections show differences in shapes among different grains and along the same grain (see FIG. 1, 6A and 6B). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “grains 51” may have different shapes as long as the diameter is near or greater than the thickness of the “electrode layer 1a” so that cracking is prevented.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the grain may have different shapes, including a second grain that has a portion that bends more than the bending portion of a first grain. The taught size helps prevent damage to the conductive pad during the wirebonding process.
Furthermore, changes in shape are held to be obvious over the prior art absent any persuasive evidence that the particular configuration of the claimed shape was significant (see MPEP 2144.4 Section B). The specification fails to disclose how the claimed shape affects the performance of semiconductor device.
Regarding claim 12, Nishimura teaches the package structure as claimed in claim 11 but fails to expressly teach wherein the second grain is not in contact with the end portion (a first “grain 51” may be at the outer edge of the contact region between “wire 2” and “electrode layer 1a”, such that an adjacent “grain 51” may not contact “wire 2” and remain exposed as suggested in FIG. 2 and 4A-4B).
Claims 2-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura as applied to claim 1 above, in view of Banik et al. US 20220010446 A1 (hereinafter referred to as Banik).
Regarding claim 2, Nishimura teaches the package structure as claimed in claim 1 but fails to teach wherein the conductive pad comprises a grain including a plurality of nanotwinned layers stacked in a direction from the substrate toward the end portion.
Nevertheless, Banik teaches a copper pillar with a high density of nanotwinned grain structures (para. 0032 FIG. 1). The grains contain stacks of nanotwins stacked along the columnar direction (para. 0033-0034). Nanotwinned copper has high strength and ductility, high electrical conductivity, high thermal stability, and a reduction in Kirkendall voids when soldering (para. 0030). Meanwhile, Nishimura teaches the “electrode layer 1a” being made of aluminum or an aluminum alloy containing copper. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that nanotwinned copper is a suitable material for use as a pad that has highly favored physical and electrical properties for forming bonds.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Nishimura with the nanotwinned copper conductive pad as taught in Banik. Nanotwinned copper is a strong, resilient, and highly conductive material used for bonding.
Regarding claim 3, Nishimura, modified by Banik, teaches the package structure as claimed in claim 2, wherein the end portion comprises a second grain contacting the crystallographic plane (since the “grains 30” of “wire 2” contact the “electrode layer 1a” now made of nanotwinned copper, it is understood the “grains 30” contact the nanotwinned grains and their crystallographic plane).
Regarding claim 9, Nishimura teaches the package structure as claimed in claim 1 but fails to teach wherein the conductive pad comprises a grain including a plurality of nanotwinned layers stacked in a direction from the substrate toward the end portion.
Nevertheless, Banik teaches a copper pillar with a high density of nanotwinned grain structures (para. 0032 FIG. 1). The grains contain stacks of nanotwins stacked along the columnar direction (para. 0033-0034). Nanotwinned copper has high strength and ductility, high electrical conductivity, high thermal stability, and a reduction in Kirkendall voids when soldering (para. 0030). Meanwhile, Nishimura teaches the “electrode layer 1a” being made of aluminum or an aluminum alloy containing copper. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that nanotwinned copper is a suitable material for use as a pad that has highly favored physical and electrical properties for forming bonds.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Nishimura with the nanotwinned copper conductive pad as taught in Banik. Nanotwinned copper is a strong, resilient, and highly conductive material used for bonding.
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US 20210043592 A1 (hereinafter referred to as Park), in view of Banik et al. US 20210043592 A1 (hereinafter referred to as Banik).
Regarding claim 13, Park teaches
A package structure (“semiconductor package 100” para. 0031 FIG. 1), comprising:
a substrate (“semiconductor substrate 101” para. 0046 FIG. 3A);
a conductive pad (“pad 180” para. 0059) disposed over the substrate and;
a first oxide layer (“metal oxide layer 140”, para. 0062) over the conductive pad;
and a conductive wire (“conductive connector 160” para. 0043) comprising an end portion penetrating the first oxide layer and contacting the anisotropic crystal structure (an end portion of “conductive connector 160” passes through “metal oxide layer 140” to connect to “pad 180”, para. 0074).
However, Park fails to teach the conductive pad having an anisotropic crystal structure.
Nevertheless, Banik teaches a copper pillar with a high density of nanotwinned grain structures (para. 0032 FIG. 1). The nanotwinned copper grains are oriented in the (111) plane and have high strength and ductility, high electrical conductivity, high thermal stability, and a reduction in Kirkendall voids when soldering (para. 0030). These properties are understood to be true for the (111) orientation. Furthermore, Chen et al. US 20140217593 A1 indicates in para. 0013 that the [111] direction, which is orthogonal to the (111) plane, has the highest self-diffusion rate, further showing anisotropy of the conductive pad. Meanwhile, Park teaches the “pad 180” being made of aluminum, copper, nickel or an alloy (para. 0059). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that nanotwinned copper is a suitable material for use as a pad that has highly favored physical and electrical properties for forming bonds.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Park with the nanotwinned copper conductive pad as taught in Banik. Nanotwinned copper is a strong, resilient, and highly conductive material used for bonding.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park’87 as applied to claim 13 above, in view of Leverrier et al. US 20020153257 A1 (hereinafter referred to as Leverrier).
Park, modified by Banik, teaches the package structure as claimed in claim 13 but fails to teach further comprising a second oxide layer covering the conductive wire, wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer.
Nevertheless, Leverrier teaches
further comprising a second oxide layer (“oxidized surface layer 44”, para. 0032 FIG. 3) covering the conductive wire (“wire 40” para. 0028).
Park, modified by Banik, and Leverrier, teach packages comprising wirebonded components.
wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer. The “wires 40” in Leverrier may be made of gold and are covered by a tantalum oxide “oxidized surface layer 44” that is highly resistant to moisture and corrosive materials (para. 0032). The “conductive connector 160” is only covered in an epoxy “encapsulation material 170” (para. 0044). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “oxidized surface layer 44” can further improve the protection of the “conductive connector 160”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure taught between Park and Banik with the second oxide taught in Leverrier. The second oxide surrounding the wire greatly enhances the protection of the wire against corrosion.
However, Park, modified by Banik and Leverrier, fail to teach a thickness of the second oxide layer is greater than a thickness of the first oxide layer.
Nevertheless, there exist three configurations regarding the thicknesses of the first and second oxide layer: they have similar thicknesses, the first has a greater thickness, or the second has greater thickness. The thickness of insulative oxide affects the amount of insulation and protection of the underlying conductor. As stated in MPEP 2143 Section E, “A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR, 550 U.S. at 421, 82 USPQ2d at 1397. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that it was obvious to try different amounts of thicknesses for the “metal oxide layer 140” in Park and the “oxidized surface layer 44” in Leverrier to achieve desired insulation of the “pad 180” and the “conductive connector 160”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a thickness of the second oxide layer greater than a thickness of the first oxide layer. It was one of a finite number of possible solutions for insulating and protecting the conductive pad and conductive wire.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US 20210043592 A1 (hereinafter referred to as Park), in view of Banik et al. US 20210043592 A1 (hereinafter referred to as Banik).
Regarding claim 17, Park teaches
A package structure (“semiconductor package 100” para. 0031 FIG. 1), comprising:
a substrate (“semiconductor substrate 101” para. 0046 FIG. 3A);
a first pad (“pad 180” para. 0059) and a second pad (“internal pad 6” para. 0034 FIG. 1) disposed over the substrate; and
a conductive wire (“conductive connector 160” para. 0043) comprising a ball portion connected to the first pad (the portion of “conductive connector 160” on “pad 180” is shown as a ball end in FIG. 3A) and a stitch portion connected to the second pad (the portion of “conductive connector 160” on “internal pad 6” is understood to be a stitch end in FIG. 1 since the portion on “pad 180” is the ball end).
However, Park fails to teach wherein the first pad comprises a first grain extending upwards from the substrate, and the second pad comprises a second grain extending upwards from the substrate, wherein the first grain comprises a first bending portion, the second grain comprises a second bending portion, and the first bending portion is more inclined than the second bending portion.
Nevertheless, Banik teaches a copper pillar with a high density of nanotwinned grain structures (para. 0032 FIG. 1). The grains are columnar, such that the grains can be said to extend upwards (para. 0032). The nanotwinned copper grains are oriented in the (111) plane and have high strength and ductility, high electrical conductivity, high thermal stability, and a reduction in Kirkendall voids when soldering (para. 0030). These properties are understood to be true for the (111) orientation. Meanwhile, Park teaches the “pad 180” being made of aluminum, copper, nickel or an alloy (para. 0059) and the “internal pad 6” is unspecified. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that nanotwinned copper is a suitable material for use as a pad that has highly favored physical and electrical properties for forming bonds.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Park with the nanotwinned copper conductive pad as taught in Banik. Nanotwinned copper is a strong, resilient, and highly conductive material used as the first and second pads.
However, Park, modified by Banik, fail to teach wherein the first grain comprises a first bending portion, the second grain comprises a second bending portion, and the first bending portion is more inclined than the second bending portion.
Nevertheless, cross sections of different examples of the nanotwinned copper pads in Banik show differences in shapes among different grains and along the same grain (see FIG. 1, 6A and 6B). Some grains have portions that bend more than in other grains despite nanotwinned grains being highly oriented. This is understood to be due to the normal process flow of crystal formation of the pads using electroplating (para. 0054-55). Despite these grain shapes, the electrical performance is still described as favorable. Furthermore, Chen et al. US 20140217593 A1 FIG. 5A-6 and Tsai et al. US 20210225793 A1 FIG. 1A and 5 show examples of nanotwinned thin films having favorable electrical properties and with grains having different shapes. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the grains may have different shapes with different degrees of bending.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the grains in the first and second pads may have bending portions of different inclinations. This is merely due to the way the nanotwinned structure forms.
Furthermore, changes in shape are held to be obvious over the prior art absent any persuasive evidence that the particular configuration of the claimed shape was significant (see MPEP 2144.4 Section B). The specification fails to disclose how the claimed shape affects the performance of semiconductor device.
Regarding claim 18, Park, modified by Banik, teaches the package structure as claimed in claim 17 but fails to expressly teach wherein the first pad comprises a plurality of first multi-layers stacked along a first direction, the second pad comprises a plurality of second multi-layers stacked along a second direction, and the first direction is more inclined than the second direction with respect to the substrate.
Nevertheless, the “pad 180” and “internal pad 6” of Park are now nanotwinned copper structures as taught in Banik. FIG. 1 in Banik shows a plurality of grains comprising stacks of nanotwins (para. 0034). Within the same conductive pad, nanotwins are stacked on slightly different directions across different grains as drawn in annotated FIG. 1 below. If this is the case within the same pad, different pads will also have grains of nanotwin stacks in different directions. A stack in “internal pad 6” that has a notable incline can be compared to a stack in “pad 180” that is less inclined. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that pads of nanotwinned copper have grains comprising nanotwins stacked in different directions. “Pad 180” and “internal pad 6” have grains of nanotwins stacked in different directions and one of the stacks in “internal pad 6” can be pointed out to be more inclined than one in “pad 180”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to define multi-layers in the first and second pad that have different stacking directions.
Furthermore, changes in shape are held to be obvious over the prior art absent any persuasive evidence that the particular configuration of the claimed shape was significant (see MPEP 2144.4 Section B). The specification fails to disclose how the claimed shape affects the performance of semiconductor device.
Regarding claim 19, Park, modified by Banik, teach the package structure as claimed in claim 17, wherein the first pad comprises a plurality of first nanotwinned layers stacked along a first [111] crystal axis (“pad 180” is modified to comprise copper nanotiwns, where “nanotwins may stack along a stacking direction (e.g., along a [111] crystal axis) to form a grain”, Banik para. 0034), the second pad comprises a plurality of second nanotwinned layers stacked along a second [111] crystal axis (“internal pad 6” is modified to comprise copper nanotiwns, where “nanotwins may stack along a stacking direction (e.g., along a [111] crystal axis) to form a grain”, Banik para. 0034).
However, Park, modified by Banik, fail to expressly teach the first [111] crystal axis and the second [111] crystal axis extend in different directions.
Nevertheless, FIG. 1 in Banik shows a plurality of grains comprising stacks of nanotwins (para. 0034). Within the same conductive pad, nanotwins are stacked on slightly different directions across different grains as drawn in annotated FIG. 1 below. If this is the case within the same pad, different pads will also have grains of nanotwin stacks in different directions and thus with their [111] axis in different directions. A stack in “internal pad 6” that has a stack with the [111] axis in one direction can be compared to a stack in “pad 180” that with their [111] axis in another direction. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that pads of nanotwinned copper have grains comprising nanotwins stacked in different directions. “Pad 180” and “internal pad 6” has grains of nanotwins with their [111] axis in different directions and one of the stacks in “internal pad 6” can be pointed out to have their [111] axis different to one in “pad 180”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to define multi-layers in the first and second pad that their [111] axis extending in different directions. This is due to their stacking directions naturally having different directions.
Furthermore, changes in shape are held to be obvious over the prior art absent any persuasive evidence that the particular configuration of the claimed shape was significant (see MPEP 2144.4 Section B). The specification fails to disclose how the claimed shape affects the performance of semiconductor device.
Allowable Subject Matter
Claims 4, 15-16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the most relevant prior art Banik et al. US 20220010446 A1 teaches grains comprising nanotwinned layer stacks. Nishimura US 20160163806 A1 teaches the wire comprising grains. However, Nishimura and Bank fail to teach or render obvious a grain of the wire end portion contacting an interface between the first nanotwinned layer and the second nanotwinned layer of the same grain. Therefore, claim 4 is considered to contain allowable subject matter.
Regarding claim 15, the most relevant prior art Park et al. US 20210043592 A1 teaches the first oxide layer formed over a top surface and lateral surface of the conductive pad. In the case of copper oxides, it is known that the crystallographic plane of the surface of a copper film has an effect on the growth of copper oxide. As evidenced in page 3440 Current Efficiency section and in Table 1 of Vvedenskii et al. “Copper oxides: kinetics of formation and semiconducting properties. Part II. Copper single crystals. J Solid State Electrochem 18”, copper oxide grows less on a (111) plane aligned crystals than other crystallographic planes such as (100) and (110). Nevertheless, “metal oxide layer 140” is taught to be aluminum oxide while “second redistribution line conductor 134” and “pad 180” may be copper. Furthermore, “metal oxide layer 140” is taught to comprise a different metal from that of “second redistribution line conductor 134”, such that it would not be obvious to modify the “metal oxide layer 140” to be a copper oxide. Park fails to render obvious a thickness of the first portion is less than a thickness of the second portion. Therefore, claim 15 is considered to contain allowable subject matter.
Regarding claim 16, the most relevant prior art Park fails to teach or render obvious a third oxide layer embedded in the anisotropic crystal structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer. Therefore, claim 16 is considered to contain allowable subject matter.
Regarding claim 20, the most relevant prior art Haga et al. US US 20150200181 A1 teaches a bonding pad with a recess that accommodates what appears to be a ball end of a wire. However, it fails to render obvious a recess in a pad for a stitch portion of a wire. Therefore, claim 20 is considered to contain allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898