Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/9/2026 have been fully considered but they are not persuasive.
Applicant's arguments filed in response to the prior action have been fully considered but are not persuasive.
1. 35 U.S.C. § 112(b) Indefiniteness & Hybrid Claim Status
Applicant contends that the independent claims define a pure product category and that the negative limitation ("wherein no seed layer is disposed between each die pad and each corresponding conductive circuit") describes a structural state of the final package. However, independent claims 1 and 10 continue to explicitly recite the complete, active manufacturing process sequence (Steps S1 through S6/S7) directly within the body of the product claims.
Reciting active method steps within a product claim creates an impermissible hybrid claim mixing two distinct statutory classes of invention. Applicant’s reliance on the process mechanics of omitting a seed layer highlights this core indefiniteness. It remains ambiguous whether an infringer breaches the claim by manufacturing the final physical package structure or by carrying out the specific step-by-step assembly sequence. The claim set fails to provide the reasonable certainty required by 35 U.S.C. § 112(b).
2. Product-by-Process Limitations & Lack of Patentable Structural Distinction (35 U.S.C. §§ 102/103)
Applicant argues that the package is structurally distinct from Scanlan and Lai because the conductive circuits are formed without a seed layer. This argument is unpersuasive.
Under MPEP § 2113, process limitations and negative process recitations in a product claim do not impart patentable weight unless they result in a physically distinct structure in the finished product. A conformal seed layer composed of the same material (e.g., copper) as the bulk conductive trace yields a continuous, monolithic metal feature in the finished device. In its final state, a solid copper trace interfacing directly with a pad or dielectric opening is structurally indistinguishable from a copper trace formed over a copper seed layer. Scanlan’s completed metal lines interfacing with die pads and dielectric layers anticipate or render obvious the claimed physical structure regardless of whether a seed layer was used during fabrication.
Furthermore, rolling the dependent limitations of nano silver/copper paste, conductive bumps, and protective layers into independent claims 1 and 10 fails to patentably distinguish the claims over Scanlan’s teachings of metallic lines, bumps, and insulating layers.
Claim Objections
Claims 1 and 10 are objected to because they are directed to a product ("chip package") but improperly include an active multi-step method of manufacturing (Steps S1 through S6/S7) within the claim body.
While the Applicant provides arguments (Remarks filed 10/9/2025) that these are "Product-by-Process Claims", the current drafting includes a formal list of method steps (Step S1 through Step S6) using procedural terminology such as "covering," "filling," and "grinding". Under 35 U.S.C. 101, a claim should be limited to a single statutory class. By reciting a complete manufacturing process within a product claim, the Applicant has created a hybrid claim that is procedurally improper.
The Applicant’s remarks explicitly state that the "structure is easily understood" and that these steps define a "Coplanar Structure". Specifically, the Applicant points to Figure 6 to show the conductive circuit is "flush with the surface of the second dielectric layer".
Because the Applicant has demonstrated that the product can be clearly described by its physical configuration (e.g., "a conductive circuit having a top surface coplanar with the second dielectric layer"), the recitation of the manufacturing steps is unnecessary. The Applicant is advised that the process steps (Steps S1-S6) should be removed, and the structural results of those steps (such as the "flush" or "coplanar" arrangement) should be integrated into the structural description of the chip package (Remarks Page 6 of 8).
Appropriate correction is required. To overcome this objection, the Applicant should:
1. Rewrite the claims to focus solely on the structural features of the finished chip package, similarly to as presented in the Remarks.
2. Relocate the manufacturing method (Steps S1-S6) to a separate Method Claim if they wish to protect the process of production.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 6, 8, 9, 10, 12, 15, 16, 18, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Hybrid Statutory Class (Apparatus vs. Method):
Independent claims 1 and 10 recite an apparatus ("A chip package comprising...") but explicitly incorporate a multi-step manufacturing method into the body of the claim ("wherein a method of manufacturing the chip package comprising the steps of: Step S1... to Step S6/S7"). A single claim that includes both an apparatus and process steps for manufacturing or using that apparatus is indefinite under 35 U.S.C. 112(b) because it leaves the scope of protection unclear—specifically, whether direct infringement occurs upon constructing/possessing the apparatus structure or upon practicing the manufacturing method steps (see IPXL Holdings, LLC v. Amazon.com, Inc., 430 F.3d 1377, 77 USPQ2d 1140 (Fed. Cir. 2005); MPEP § 2173.05(p)(II)).
Conflicting State of Matter / Scope of Claimed Structure:
Independent claims 1 and 10 recite that the conductive circuit is formed by "highly concentrated silver paste or copper paste" or "nano silver paste or nano copper paste" disposed within the grooves. However, the claims simultaneously recite finished package features, such as conductive bumps, third dielectric layers, bonding pads, and optional solder balls or wire bonds. It is unclear whether the claims are directed to:
An intermediate, uncompleted manufacturing state where the conductive material remains an uncured "paste."
A finished, operational chip package (where liquid/uncured paste cannot physically exist to support solder reflow or operational interconnections).
The process steps themselves.
This ambiguity renders the physical boundaries and statutory scope of claims 1 and 10 (and dependent claims 3, 6, 8, 9, 12, 15, 16, 18, and 19) completely indefinite.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3, 6, 8, 9, 10, 12, 15, 16, 18, and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Written Description Requirement: To the extent claims 1 and 10 are construed as an apparatus defining a finished, operational chip package wherein the conductive circuit traces remain in an uncured or liquid "paste" state, the specification fails to provide adequate written description support under 35 U.S.C. 112(a). The specification contains no description or teaching of a functional microelectronic package utilizing uncured paste as its permanent, final conductive circuit layer.
Enablement Requirement: The specification fails to enable one skilled in the art to make and use a finished chip package containing uncured conductive paste traces without undue experimentation. The specification provides no guidance or structural enabling detail on how an uncured paste matrix could withstand subsequent planarization/grinding (Step S5/S6), dielectric layer deposition, or thermal solder ball reflow (Claim 8/18) while maintaining trace integrity and electrical isolation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6, 8, 10, 12, 15, 16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Scanlan et al. (WO 2015138359 A1).
Regarding the product by process and functorial limitations of the claims, the device of Scanlan teaches the structure of the claimed invention, and the steps of forming are not understood to provide any clear distinction as this is the general definition of the product. Therefore, the claimed invention is anticipated under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, the process of forming is obvious under 35 U.S.C. 103 over Scanlan et al.
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CLAIM 1: Scanlan teaches a chip package comprising:
a chip 24 having a surface (side with layer 36) (Fig. 6 & 4),
a at least one die pad (Fig. 6 – 44 or alternatively Fig. 4 - 32) disposed on the surface, and at least one chip protection layer arranged at the surface (Fig. 6 – 62 or alternatively Fig. 4 - 36);
wherein the chip is formed by cutting of a wafer (This steps is not understood to provide any clear distinction as this is the general definition of chip/die.); at least one first dielectric layer (Fig. 6 – 62 or alternatively Fig. 4 – 36 )which is covering a surface of the chip protection layer of the chip and provided with at least one first groove by which the die pad is exposed (Fig. 6 & 4 – Functional and product-by-process language fails to provide a clear structural distinction over the prior art. Specifically, the pending claims do not distinguish between a “protection layer” and a “first dielectric,” as a single material may possess regions serving both roles. Both layers function as dielectric materials, providing simultaneous insulation and protection. Furthermore, Scanlan explicitly teaches in paragraph [48] that “insulating layer 36 can be an organic or inorganic layer and contain one or more layers.” Therefore, as illustrated in Figure 6 of Scanlan, layer 36 encompasses the scope of two distinct layers, even if not explicitly labeled as such. );
at least one second dielectric (Fig. 6 – 162 or alternatively Fig. 4 - 62) layer which is covering a surface of the first dielectric layer and is provided with at least one second groove which is communicating with the first groove of the first dielectric layer (Fig. 6 – 162 or alternatively Fig. 4 - 62);
at least one conductive circuit (e.g. the metallization layers) disposed in the first groove and the second groove and electrically connected with the die pad wherein no seed layer is disposed between each die pad and each corresponding conductive circuit (A seed layer is a thin, hidden starting coat of metal that helps the main metal stick, but it does not change the final shape or structure of the object.) ; wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste; wherein the surface of the conductive circuit is further electrically connected and provided with at least one conductive bump; wherein at least one first protective layer is electrically connected with and arranged over the conductive bump (Fig. 6 or alternatively Fig. 4 - ¶75 discloses metals such as copper. The current product-by-process limitation lacks clarity as to whether the claimed structure is finished or unfinished. As best understood, the recitation of a "paste" implies a process that results in a cured, finished metal structure suitable for an operable device. Furthermore, this final copper structure would have been obvious to a PHOSITA in view of the prior art.);
wherein at least one second protective layer is electrically connected with and disposed over the first protective layer (Fig. 6 – 162 or alternatively Fig. 4 - 62);
at least one third dielectric layer (Fig. 6 – 166 or alternatively Fig. 4 - 134); covering both a surface of the second dielectric layer and a surface of the conductive circuit and provided with at least one opening by which the conductive circuit is exposed (Fig. 6 or alternatively Fig. 4); at least one bonding pad is formed on the conductive circuit and corresponding to the opening for electrical connection to the outside (Fig. 6 – electrical connection 168 or alternatively Fig. 4 electrical connection 136);
wherein a method of manufacturing the chip package comprising the steps of:
Step S1: providing a chip which is provided with a plurality of chips arranged in an array and each of the chips having a surface, at least one die pad arranged at the surface, and at least one chip protection layer disposed on the surface (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S2: covering a surface of the chip protection layer of the chip with at least one first dielectric layer on which at least one first groove is formed and the die pad is exposed by the first groove (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S3: covering a surface of the first dielectric layer with at least one second dielectric layer on which at least one second groove is formed and the second groove is communicating with the first groove of the first dielectric layer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S4: filling highly concentrated silver paste or copper paste into the first groove and the second groove while a surface of the highly concentrated silver paste or copper paste is at a higher level than a surface of the second dielectric layer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste (Fig. 6 or alternatively Fig. 4 - ¶75 discloses metals such as copper. The current product-by-process limitation lacks clarity as to whether the claimed structure is finished or unfinished. As best understood, the recitation of a "paste" implies a process that results in a cured, finished metal structure suitable for an operable device. Furthermore, this final copper structure would have been obvious to a PHOSITA in view of the prior art.);
Step S5: grinding the highly concentrated silver paste or copper paste having the surface at the higher level than the surface of the second dielectric layer until the surface of the second dielectric layer is exposed and the surface of the highly concentrated silver paste or copper paste is flush with the surface of the second dielectric layer to form at least one conductive circuit (Fig. 6 or alternatively Fig. 4 – The procedural or functional language used does not impart any additional structural distinctions beyond those previously addressed. In the prior art, the respective conductive layers are shown to be coplanar with their corresponding dielectric layers. Furthermore, various alternative embodiments, while not explicitly cited as a basis for rejection, demonstrate the established capability of forming Redistribution Layers (RDL) (e.g., vias and traces), Under-Bump Metallization (UBM) layers (e.g., pads), and contacts through buildup processes. These processes, which may or may not include planarization steps, consistently result in features that are flush or coplanar with the adjacent insulation and dielectric layers.); wherein the die pad is electrically connected with the conductive circuit (Fig. 6), wherein no seed layer is disposed between each die pad and each corresponding conductive circuit (A seed layer is a thin, hidden starting coat of metal that helps the main metal stick, but it does not change the final shape or structure of the object.); and
Step S6: covering the surface of the second dielectric layer and a surface of the conductive circuit with at least one third dielectric layer which is provided with at least one opening for allowing the conductive circuit to be exposed; wherein at least one bonding pad is formed on the conductive circuit and corresponding to the opening for external electrical connection; wherein the surface of the conductive circuit is further electrically connected and provided with at least one conductive bump; wherein at least one first protective layer is electrically connected with and arranged over the conductive bump; wherein at least one second protective layer is electrically connected with and disposed over the first protective layer (Fig. 6 or alternatively Fig. 4)
CLAIM 3. Scanlan teaches a chip package as claimed in claim 2, wherein the conductive bump is a bump formed by a nickel (Ni) layer and a gold (Au) layer, a bump formed by a palladium (P) layer and a gold (Au) layer, or a bump formed by a nickel (Ni) layer, a palladium (P) layer, and a gold (Au) layer (Fig. 6 or alternatively Fig. 4 & ¶95).
CLAIM 6. Scanlan teaches a chip package as claimed in claim 1, wherein a total thickness of a combination of the first dielectric layer, the second dielectric layer, the conductive circuit, and the third dielectric layer stacked over each other is 25 micrometers (μm) (Fig. 6 or alternatively Fig. 4 & ¶51 provides a range that encompasses the specific thickness point in the claim. Therefore, the explicitly defined thickness is an obvious option to a PHOSITA.).
CLAIM 7. Scanlan teaches a chip package as claimed in claim 1, wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.)
CLAIM 8. Scanlan teaches a chip package as claimed in claim 1, wherein at least one solder ball is arranged at the opening of the third dielectric layer so that the conductive circuit is electrically connected to the outside by the solder ball Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.)
CLAIM 10. Scanlan teaches a chip package comprising: a chip having a surface, a at least one die pad disposed on the surface, and at least one chip protection layer arranged at the surface (Fig. 6 or alternatively Fig. 4);
wherein the chip is formed by cutting of a wafer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
at least one first dielectric layer which is covering a surface of the chip protection layer of the chip and provided with at least one first groove by which the die pad is exposed (Fig. 6 or alternatively Fig. 4);
at least one die-pad bump formed in the first groove, located on a surface of the die pad, and electrically connected with the die pad (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
at least one second dielectric layer which is covering a surface of the first dielectric layer and is provided with at least one second groove which is communicating with the first groove of the first dielectric layer (Fig. 6 or alternatively Fig. 4.);
at least one conductive circuit disposed within the second groove and electrically connected with the die pad bump; wherein no seed layer is disposed between each die pad and each corresponding conductive circuit; wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste; wherein the surface of the conductive circuit is provided with at least one conductive bump and the conductive bump is electrically connected with the conductive circuit; wherein at least one first protective layer is electrically connected with and arranged over the conductive bump; wherein at least one second protective layer is electrically connected with and disposed over the first protective layer; (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.); and
at least one third dielectric layer covering both a surface of the second dielectric layer and a surface of the conductive circuit and provided with at least one opening by which the conductive circuit is exposed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
at least one bonding pad is formed on the conductive circuit and corresponding to the opening for external electrical connection (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein a method of manufacturing the chip package comprising the steps of: Step S1: providing a chip which is provided with a plurality of chips arranged in an array and each of the chips having a surface, at least one die pad arranged at the surface, and at least one chip protection layer disposed on the surface (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S2: covering a surface of the chip protection layer of the chip with at least one first dielectric layer on which at least one first groove is formed and the die pad is exposed by the first groove (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S3: forming at least one die-pad bump in the first groove while the die-pad bump is located on a surface of the die pad and electrically connected with the die pad (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S4: covering a surface of the first dielectric layer with at least one second dielectric layer on which at least one second groove is formed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
the second groove is communicating with the first groove of the first dielectric layer (Fig. 6 or alternatively Fig. 4);
Step S5: filling highly concentrated silver paste or copper paste into the first groove and the second groove while a level of the highly concentrated silver paste or copper paste is higher than a surface of the second dielectric layer wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste; (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S6: grinding the highly concentrated silver paste or copper paste with the level higher than the surface of the second dielectric layer so that the surface of the second dielectric layer is exposed and a surface of the highly concentrated silver paste or copper paste is flush with the surface of the second dielectric layer to form at least one conductive circuit (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein the die-pad bump is electrically connected with the conductive circuit; wherein no seed layer is disposed between each die pad and each corresponding conductive circuit; and (Fig. 6 or alternatively Fig. 4); and
Step S7: covering a surface of the second dielectric layer and a surface of the conductive circuit with at least one third dielectric layer which is provided with at least one opening for allowing the conductive circuit to be exposed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein at least one bonding pad is formed on the conductive circuit and corresponding to the opening for external electrical connection (Fig. 6 or alternatively Fig. 4) wherein the surface of the conductive circuit is provided with at least one conductive bump and the conductive bump is electrically connected with the conductive circuit; wherein at least one first protective layer is electrically connected with and arranged over the conductive bump; wherein at least one second protective layer is electrically connected with and disposed over the first protective layer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.).
CLAIM 12. Scanlan teaches a chip package as claimed in claim 11, wherein the conductive bump is a bump formed by a nickel (Ni) layer and a gold (Au) layer, or a bump formed by a palladium (Pd) layer and a gold (Au) layer, or a bump formed by a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer (Fig. 6 or alternatively Fig. 4 & ¶95).
CLAIM 15. Scanlan teaches a chip package as claimed in claim 10, wherein the die-pad bump is a bump formed by a nickel (Ni) layer and a gold (Au) layer, or a bump formed by a palladium (Pd) layer and a gold (Au) layer, or a bump formed by a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer (Fig. 6 or alternatively Fig. 4 & ¶95).
CLAIM 16. Scanlan teaches a chip package as claimed in claim 10, wherein a total thickness of a combination of the first dielectric layer, the second dielectric layer, the conductive circuit, and the third dielectric layer stacked over each other is 25 micrometers (μm). (Fig. 6 or alternatively Fig. 4 & ¶51 provides a range that encompasses the specific thickness point in the claim. Therefore, the explicitly defined thickness is an obvious option to a PHOSITA.).
CLAIM 18. Scanlan teaches a chip package as claimed in claim 6, wherein at least one solder ball is arranged at the opening of the third dielectric layer so that the conductive circuit is electrically connected to the outside by the solder ball (Fig. 6 or alternatively Fig. 4).
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as obvious over Scanlan et al. (WO 2015138359 A1) in view of Lai et al (US 20130320522 A1).
CLAIM 9. Scanlan teaches a chip package as claimed in claim 1. The further limitation of wherein a first bonding point and a second bonding point are respectively formed on the conductive circuit in the opening and an electronic component by a bonding wire used in wire bonding to form electrical connection between the chip package and the electronic component is not understood to impart any further structural distinction from the claimed chip package.
Claim 1 is directed to a chip package. As defined in paragraph [0044] of the Applicant’s written description, the "electronic component" is a separate device outside the scope of the package that is merely "capable" of being wire-bonded to the claimed package. While Scanlan is silent regarding wire-bonding as an alternative electrical connection, it discloses the same required structure as claimed.
At the time of the invention, it was common knowledge to a PHOSITA that wire bonding is a functional equivalent to solder bumps, solder balls, or other standard electrical connections used to interface a package with external components. Lai teaches analogous RDL buildup levels that lead to an external connection pad. As shown in Figures 1A and 1C of Lai, such pads are known to be compatible with either wire bonds or solder bonds. This confirms the state of the art: a PHOSITA would have found it obvious to connect the pads of Scanlan to external components via wire bonding if desired.
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When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
CLAIM 19. Scanlan teaches a chip package as claimed in claim 6. The further limitation of wherein a first bonding point and a second bonding point are respectively formed on the conductive circuit in the opening and an electronic component by a bonding wire used in wire bonding to form electrical connection between the chip package and the electronic component is not understood to impart any further structural distinction from the claimed chip package.
Claim 10 is directed to a chip package. As defined in paragraph [0044] of the Applicant’s written description, the "electronic component" is a separate device outside the scope of the package that is merely "capable" of being wire-bonded to the claimed package. While Scanlan is silent regarding wire-bonding as an alternative electrical connection, it discloses the same required structure as claimed.
At the time of the invention, it was common knowledge to a PHOSITA that wire bonding is a functional equivalent to solder bumps, solder balls, or other standard electrical connections used to interface a package with external components. Lai teaches analogous RDL buildup levels that lead to an external connection pad. As shown in Figures 1A and 1C of Lai, such pads are known to be compatible with either wire bonds or solder bonds. This confirms the state of the art: a PHOSITA would have found it obvious to connect the pads of Scanlan to external components via wire bonding if desired.
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When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/24/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
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