Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/9/2026 have been fully considered but they are not persuasive.
1. Failure to Meet the Necessity of Product-by-Process Drafting
The Applicant asserts that these claims are "Product-by-Process Claims" under MPEP § 2113. However, this format is generally reserved for inventions that are physically incapable of being described by their structure1. The Applicant’s own argument defeats this necessity by stating that the process steps "directly define the Coplanar Structure" (Remarks Page 6 of 8) and that the structure can be understood "unambiguously" from the description (Page 6 of 8).
If the final product is a circuit that is "flush with the surface of the second dielectric layer" (Remarks Page 6 of 8), that is a physical, structural relationship. Because this "coplanar" state can be described using standard structural language, reciting the active method of "grinding... until the surface... is exposed" (Remarks Page 6 of 8) is unnecessary and serves only to muddy the statutory boundaries of the claim.
The Applicant argues that the process description essentially constitutes a "further limitation on the product structure" rather than protection of the method itself (Remarks Page 7 of 8). However, Claim 1, instead of using a short modifying adjective to suggest the structure, it provides a comprehensive, six-step manufacturing sequence.
This creates a "hybrid" claim that is indefinite because, as previously noted by the Examiner (Remarks Page 2 of 8), it remains unclear whether a competitor would infringe by:
1) Manufacturing the final chip package.
2) Performing the specific "filling" and "grinding" steps recited in S4 and S5.
The Applicant acknowledges that for infringement purposes, an product must be made by the specific process recited (Remarks, Top of Page 4 of 8). This highlights the ambiguity: the claim attempts to protect a physical object while simultaneously restricting that protection to a specific sequence of acts. This lack of clarity fails to provide the "reasonable certainty" required by 35 U.S.C. 112(b), with is the basis of the rejection for indefiniteness.
The Applicant cites In re Garnero and In re Nordt Dev. Co. to justify process-based terms (Remarks Page 4 of 8). Those cases addressed terms like "interbonded" or "injection molded" which describe a finished state. Whereas, the Applicant is reciting active manipulations—specifically the act of "grinding... until the surface... is exposed" (Remarks Page 6 of 8). This is a procedural instruction, not a structural result.
The Applicant further points to the allowance of US 2023/0395538 A1 as evidence of acceptability (Remarks Page 7 of 8). However, each application is examined on its own merits. The fact that a different examiner may have allowed similar language does not cure the indefiniteness present in this specific claim set, where the structural boundaries are obscured by a lengthy method description.
Because the Applicant has demonstrated that the product can be described structurally; specifically, as a "Coplanar Structure" (Remarks Page 6 of 8); the use of a process-heavy "Product-by-Process" claim is improper and indefinite. The rejection is maintained.
Claim Objections
Claims 1 and 10 are objected to because they are directed to a product (a "chip package") but improperly include a multi-step "method of manufacturing" within the body of the claim.
While the Applicant provides arguments (Remarks filed 10/9/2025) that these are "Product-by-Process Claims", the current drafting includes a formal list of method steps (Step S1 through Step S6) using procedural terminology such as "covering," "filling," and "grinding". Under 35 U.S.C. 101, a claim should be limited to a single statutory class. By reciting a complete manufacturing process within a product claim, the Applicant has created a hybrid claim that is procedurally improper.
The Applicant’s remarks explicitly state that the "structure is easily understood" and that these steps define a "Coplanar Structure". Specifically, the Applicant points to Figure 6 to show the conductive circuit is "flush with the surface of the second dielectric layer".
Because the Applicant has demonstrated that the product can be clearly described by its physical configuration (e.g., "a conductive circuit having a top surface coplanar with the second dielectric layer"), the recitation of the manufacturing steps is unnecessary. The Applicant is advised that the process steps (Steps S1-S6) should be removed, and the structural results of those steps (such as the "flush" or "coplanar" arrangement) should be integrated into the structural description of the chip package (Remarks Page 6 of 8).
Appropriate correction is required. To overcome this objection, the Applicant should:
1. Rewrite the claims to focus solely on the structural features of the finished chip package, similarly to as presented in the Remarks.
2. Relocate the manufacturing method (Steps S1-S6) to a separate Method Claim if they wish to protect the process of production.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims [specifically claims 1 and 10] attempts to define both a chip package (a product or apparatus) and a method of manufacturing that package (a process) within a single claim. This is considered indefinite because it mixes two distinct statutory classes of invention. A single claim that claims both a device and the method of manufacturing is indefinite under 35 U.S.C. 112(b).
Combining these two different types of inventions (product and process) into one claim makes it unclear to the public what exactly is being protected. It is difficult to determine whether infringement occurs when someone makes the chip package, or when someone performs the manufacturing steps, or both. This lack of clarity means the claim does not particularly point out and distinctly claim the subject matter which the inventor regards as the invention, and therefore fails to meet the definiteness requirement of 35 U.S.C. 112(b). The claims must be sufficiently precise to inform those skilled in the art about the scope of the invention with reasonable certainty.
Claim Interpretation
In view the Applicant’s remarks dated 10/7/2025, the current Office Action will not be made final. Instead, a new rejection based on prior art is presented to promote compact prosecution and to provide the Applicant an opportunity to address the structural merits of the invention . For the purpose of this examination, the “chip package” of Claim 1 is interpreted as a product defined by the structural results of the recited proc ess steps, consistent with the Applicant’s argument that these steps “directly define the Coplanar Structure” (Remarks Page 6 of 8). Specifically, the conductive circuit is constructed as a structural feature where the conductive paste is “flush with the surface of the second dielectric layer,” as illustrated in the Applicant’s Fig. 6 and described as the “critical structure feature” (Remarks Page 6 of 8). This interpretation treats the “grinding” and “filling” steps not as procedure requirements, but as functional descriptors of the finished physical state of the package.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-18 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Scanlan et al. (WO 2015138359 A1).
Regarding the product by process and functorial limitations of the claims, the device of Scanlan teaches the structure of the claimed invention, and the steps of forming are not understood to provide any clear distinction as this is the general definition of the product. Therefore, the claimed invention is anticipated under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, the process of forming is obvious under 35 U.S.C. 103 over Scanlan et al.
PNG
media_image1.png
219
717
media_image1.png
Greyscale
CLAIM 1: Scanlan teaches a chip package comprising:
a chip 24 having a surface (side with layer 36) (Fig. 6 & 4),
a at least one die pad (Fig. 6 – 44 or alternatively Fig. 4 - 32) disposed on the surface, and at least one chip protection layer arranged at the surface (Fig. 6 – 62 or alternatively Fig. 4 - 36);
wherein the chip is formed by cutting of a wafer (This steps is not understood to provide any clear distinction as this is the general definition of chip/die.); at least one first dielectric layer (Fig. 6 – 62 or alternatively Fig. 4 – 36 )which is covering a surface of the chip protection layer of the chip and provided with at least one first groove by which the die pad is exposed (Fig. 6 & 4 – Functional and product-by-process language fails to provide a clear structural distinction over the prior art. Specifically, the pending claims do not distinguish between a “protection layer” and a “first dielectric,” as a single material may possess regions serving both roles. Both layers function as dielectric materials, providing simultaneous insulation and protection. Furthermore, Scanlan explicitly teaches in paragraph [48] that “insulating layer 36 can be an organic or inorganic layer and contain one or more layers.” Therefore, as illustrated in Figure 6 of Scanlan, layer 36 encompasses the scope of two distinct layers, even if not explicitly labeled as such. );
at least one second dielectric (Fig. 6 – 162 or alternatively Fig. 4 - 62) layer which is covering a surface of the first dielectric layer and is provided with at least one second groove which is communicating with the first groove of the first dielectric layer (Fig. 6 – 162 or alternatively Fig. 4 - 62); at least one conductive circuit (e.g. the metallization layers) which is formed by highly concentrated silver paste or copper paste filled in the first groove and the second groove and electrically connected with the die pad (Fig. 6 or alternatively Fig. 4 - ¶75 discloses metals such as copper. The current product-by-process limitation lacks clarity as to whether the claimed structure is finished or unfinished. As best understood, the recitation of a "paste" implies a process that results in a cured, finished metal structure suitable for an operable device. Furthermore, this final copper structure would have been obvious to a PHOSITA in view of the prior art.);
at least one third dielectric layer (Fig. 6 – 166 or alternatively Fig. 4 - 134); covering both a surface of the second dielectric layer and a surface of the conductive circuit and provided with at least one opening by which the conductive circuit is exposed (Fig. 6 or alternatively Fig. 4); at least one bonding pad is formed on the conductive circuit and corresponding to the opening for electrical connection to the outside (Fig. 6 – electrical connection 168 or alternatively Fig. 4 electrical connection 136);
wherein a method of manufacturing the chip package comprising the steps of:
Step S1: providing a chip which is provided with a plurality of chips arranged in an array and each of the chips having a surface, at least one die pad arranged at the surface, and at least one chip protection layer disposed on the surface (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S2: covering a surface of the chip protection layer of the chip with at least one first dielectric layer on which at least one first groove is formed and the die pad is exposed by the first groove (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S3: covering a surface of the first dielectric layer with at least one second dielectric layer on which at least one second groove is formed and the second groove is communicating with the first groove of the first dielectric layer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S4: filling highly concentrated silver paste or copper paste into the first groove and the second groove while a surface of the highly concentrated silver paste or copper paste is at a higher level than a surface of the second dielectric layer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S5: grinding the highly concentrated silver paste or copper paste having the surface at the higher level than the surface of the second dielectric layer until the surface of the second dielectric layer is exposed and the surface of the highly concentrated silver paste or copper paste is flush with the surface of the second dielectric layer to form at least one conductive circuit (Fig. 6 or alternatively Fig. 4 – The procedural or functional language used does not impart any additional structural distinctions beyond those previously addressed. In the prior art, the respective conductive layers are shown to be coplanar with their corresponding dielectric layers. Furthermore, various alternative embodiments, while not explicitly cited as a basis for rejection, demonstrate the established capability of forming Redistribution Layers (RDL) (e.g., vias and traces), Under-Bump Metallization (UBM) layers (e.g., pads), and contacts through buildup processes. These processes, which may or may not include planarization steps, consistently result in features that are flush or coplanar with the adjacent insulation and dielectric layers.);
wherein the die pad is electrically connected with the conductive circuit (Fig. 6 or alternatively Fig. 4); and
Step S6: covering the surface of the second dielectric layer and a surface of the conductive circuit with at least one third dielectric layer which is provided with at least one opening for allowing the conductive circuit to be exposed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.); wherein at least one bonding pad is formed on the conductive circuit and corresponding to the opening for external electrical connection (Fig. 6 – electrical connection 168 or alternatively Fig. 4 electrical connection 136).
CLAIM 2. Scanlan teaches a chip package as claimed in claim 1, wherein the surface of the conductive circuit is further electrically connected and provided with at least one conductive bump (Fig. 6 or alternatively Fig. 4).
CLAIM 3. Scanlan teaches a chip package as claimed in claim 2, wherein the conductive bump is a bump formed by a nickel (Ni) layer and a gold (Au) layer, a bump formed by a palladium (P) layer and a gold (Au) layer, or a bump formed by a nickel (Ni) layer, a palladium (P) layer, and a gold (Au) layer (Fig. 6 or alternatively Fig. 4 & ¶95).
CLAIM 4. Scanlan teaches a chip package as claimed in claim 2, wherein at least one first protective layer is electrically connected with and arranged over the conductive bump (Fig. 6 or alternatively Fig. 4).
CLAIM 5. Scanlan teaches a chip package as claimed in claim 4, wherein at least one second protective layer is electrically connected with and disposed over the first protective layer (Fig. 6 or alternatively Fig. 4 – The functional language does not provide any further distinction over the insulation/dielectric layers as they are understood to perform the same function. The language does not require the layers to be distinct, which is consistent with Applicant’s Fig. 6.).
CLAIM 6. Scanlan teaches a chip package as claimed in claim 1, wherein a total thickness of a combination of the first dielectric layer, the second dielectric layer, the conductive circuit, and the third dielectric layer stacked over each other is 25 micrometers (μm) (Fig. 6 or alternatively Fig. 4 & ¶51 provides a range that encompasses the specific thickness point in the claim. Therefore, the explicitly defined thickness is an obvious option to a PHOSITA.).
CLAIM 7. Scanlan teaches a chip package as claimed in claim 1, wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.)
CLAIM 8. Scanlan teaches a chip package as claimed in claim 1, wherein at least one solder ball is arranged at the opening of the third dielectric layer so that the conductive circuit is electrically connected to the outside by the solder ball Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.)
CLAIM 10. Scanlan teaches a chip package comprising: a chip having a surface, a at least one die pad disposed on the surface, and at least one chip protection layer arranged at the surface (Fig. 6 or alternatively Fig. 4);
wherein the chip is formed by cutting of a wafer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
at least one first dielectric layer which is covering a surface of the chip protection layer of the chip and provided with at least one first groove by which the die pad is exposed (Fig. 6 or alternatively Fig. 4);
at least one die-pad bump formed in the first groove, located on a surface of the die pad, and electrically connected with the die pad (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
at least one second dielectric layer which is covering a surface of the first dielectric layer and is provided with at least one second groove which is communicating with the first groove of the first dielectric layer (Fig. 6 or alternatively Fig. 4.);
at least one conductive circuit which is formed by highly concentrated silver paste or copper paste filled in the first groove and the second groove and electrically connected with the die pad (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.); and
at least one third dielectric layer covering both a surface of the second dielectric layer and a surface of the conductive circuit and provided with at least one opening by which the conductive circuit is exposed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
at least one bonding pad is formed on the conductive circuit and corresponding to the opening for external electrical connection (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein a method of manufacturing the chip package comprising the steps of: Step S1: providing a chip which is provided with a plurality of chips arranged in an array and each of the chips having a surface, at least one die pad arranged at the surface, and at least one chip protection layer disposed on the surface (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S2: covering a surface of the chip protection layer of the chip with at least one first dielectric layer on which at least one first groove is formed and the die pad is exposed by the first groove (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S3: forming at least one die-pad bump in the first groove while the die-pad bump is located on a surface of the die pad and electrically connected with the die pad (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S4: covering a surface of the first dielectric layer with at least one second dielectric layer on which at least one second groove is formed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
the second groove is communicating with the first groove of the first dielectric layer (Fig. 6 or alternatively Fig. 4);
Step S5: filling highly concentrated silver paste or copper paste into the first groove and the second groove while a level of the highly concentrated silver paste or copper paste is higher than a surface of the second dielectric layer (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
Step S6: grinding the highly concentrated silver paste or copper paste with the level higher than the surface of the second dielectric layer so that the surface of the second dielectric layer is exposed and a surface of the highly concentrated silver paste or copper paste is flush with the surface of the second dielectric layer to form at least one conductive circuit (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein the die-pad bump is electrically connected with the conductive circuit (Fig. 6 or alternatively Fig. 4); and
Step S7: covering a surface of the second dielectric layer and a surface of the conductive circuit with at least one third dielectric layer which is provided with at least one opening for allowing the conductive circuit to be exposed (Fig. 6 or alternatively Fig. 4 – The procedural/functional language is not understood to impart any further structural distinction from as addressed above.);
wherein at least one bonding pad is formed on the conductive circuit and corresponding to the opening for external electrical connection (Fig. 6 or alternatively Fig. 4).
CLAIM 11. Scanlan teaches a chip package as claimed in claim 10, wherein the surface of the conductive circuit is provided with at least one conductive bump and the conductive bump is electrically connected with the conductive circuit (Fig. 6 or alternatively Fig. 4).
CLAIM 12. Scanlan teaches a chip package as claimed in claim 11, wherein the conductive bump is a bump formed by a nickel (Ni) layer and a gold (Au) layer, or a bump formed by a palladium (P) layer and a gold (Au) layer, or a bump formed by a nickel (Ni) layer, a palladium (P) layer, and a gold (Au) layer (Fig. 6 or alternatively Fig. 4 & ¶95).
CLAIM 13. Scanlan teaches a chip package as claimed in claim 11, wherein at least one first protective layer is electrically connected with and arranged over the conductive bump (Fig. 6 or alternatively Fig. 4).
CLAIM 14. Scanlan teaches a chip package as claimed in claim 13, wherein at least one second protective layer is electrically connected with and disposed over the first protective layer (Fig. 6 or alternatively Fig. 4).
CLAIM 15. Scanlan teaches a chip package as claimed in claim 10, wherein the die-pad bump is a bump formed by a nickel (Ni) layer and a gold (Au) layer, or a bump formed by a palladium (P) layer and a gold (Au) layer, or a bump formed by a nickel (Ni) layer, a palladium (P) layer, and a gold (Au) layer (Fig. 6 or alternatively Fig. 4 & ¶95).
CLAIM 16. Scanlan teaches a chip package as claimed in claim 10, wherein a total thickness of a combination of the first dielectric layer, the second dielectric layer, the conductive circuit, and the third dielectric layer stacked over each other is 25 micrometers (μm). (Fig. 6 or alternatively Fig. 4 & ¶51 provides a range that encompasses the specific thickness point in the claim. Therefore, the explicitly defined thickness is an obvious option to a PHOSITA.).
CLAIM 17. Scanlan teaches a chip package as claimed in claim 10, wherein highly concentrated silver paste or copper paste which forms the conductive circuit is nano silver paste or nano copper paste (Fig. 6 or alternatively Fig. 4).
CLAIM 18. Scanlan teaches a chip package as claimed in claim 10, wherein at least one solder ball is arranged at the opening of the third dielectric layer so that the conductive circuit is electrically connected to the outside by the solder ball (Fig. 6 or alternatively Fig. 4).
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as obvious over Scanlan et al. (WO 2015138359 A1) in view of Lai et al (US 20130320522 A1).
CLAIM 9. Scanlan teaches a chip package as claimed in claim 1. The further limitation of wherein a first bonding point and a second bonding point are respectively formed on the conductive circuit in the opening and an electronic component by a bonding wire used in wire bonding to form electrical connection between the chip package and the electronic component is not understood to impart any further structural distinction from the claimed chip package.
Claim 1 is directed to a chip package. As defined in paragraph [0044] of the Applicant’s written description, the "electronic component" is a separate device outside the scope of the package that is merely "capable" of being wire-bonded to the claimed package. While Scanlan is silent regarding wire-bonding as an alternative electrical connection, it discloses the same required structure as claimed.
At the time of the invention, it was common knowledge to a PHOSITA that wire bonding is a functional equivalent to solder bumps, solder balls, or other standard electrical connections used to interface a package with external components. Lai teaches analogous RDL buildup levels that lead to an external connection pad. As shown in Figures 1A and 1C of Lai, such pads are known to be compatible with either wire bonds or solder bonds. This confirms the state of the art: a PHOSITA would have found it obvious to connect the pads of Scanlan to external components via wire bonding if desired.
PNG
media_image2.png
450
752
media_image2.png
Greyscale
PNG
media_image3.png
430
760
media_image3.png
Greyscale
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
CLAIM 19. Scanlan teaches a chip package as claimed in claim 10. The further limitation of wherein a first bonding point and a second bonding point are respectively formed on the conductive circuit in the opening and an electronic component by a bonding wire used in wire bonding to form electrical connection between the chip package and the electronic component is not understood to impart any further structural distinction from the claimed chip package.
Claim 10 is directed to a chip package. As defined in paragraph [0044] of the Applicant’s written description, the "electronic component" is a separate device outside the scope of the package that is merely "capable" of being wire-bonded to the claimed package. While Scanlan is silent regarding wire-bonding as an alternative electrical connection, it discloses the same required structure as claimed.
At the time of the invention, it was common knowledge to a PHOSITA that wire bonding is a functional equivalent to solder bumps, solder balls, or other standard electrical connections used to interface a package with external components. Lai teaches analogous RDL buildup levels that lead to an external connection pad. As shown in Figures 1A and 1C of Lai, such pads are known to be compatible with either wire bonds or solder bonds. This confirms the state of the art: a PHOSITA would have found it obvious to connect the pads of Scanlan to external components via wire bonding if desired.
PNG
media_image2.png
450
752
media_image2.png
Greyscale
PNG
media_image3.png
430
760
media_image3.png
Greyscale
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/25/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
1 In re Garnero, 412 F.2d 276 (CCPA 1969), and corresponding guidance in MPEP § 2113, a product-by-process limitation is particularly relevant, and given weight in patentability determinations, when the product can only be defined by the process steps, or when the process steps impart a unique, identifiable structure to the final product.