Office Action Predictor
Last updated: April 16, 2026
Application No. 18/207,875

INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME

Non-Final OA §102§103§112
Filed
Jun 09, 2023
Examiner
PHAM, THANHHA S
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, LTD.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
89%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
742 granted / 872 resolved
+17.1% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
894
Total Applications
across all art units

Statute-Specific Performance

§103
33.5%
-6.5% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
23.5%
-16.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 872 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office Action is in response to Applicant’s Amendment dated 10/7/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. ► With respect to claim 9, “ the second etch layer” and “the first etch layer” lacking antecedent basis render the claim indefinite. It is not clear where “the second etch layer” and “the first etch layer” come from and are located. ***Suggestion: change “the second etch layer” and “the first etch layer” to “the second etch stop layer” and “the first etch stop layer” respectively as consistent claimed language to define scope of claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – Claims 1-3, 8-9 a re rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" [ (a)(1) as being anticipated by Hsueh et al [US 2021/0098290] ► With respect to claim 1, Hsueh et al (figs 1-17B, text [0001] -[ 0053]) discloses the claimed method for forming a semiconductor device structure, comprising: forming one or more first conductive features (210A or 210B, fig 2, text [0020]) in a first dielectric laye r (208) ; forming a metal layer (214, fig 3, text [0021]) on each of the one or more first conductive features; forminq a pre-layer (218, fig 5) on the metal layer; forming a first etch stop layer (220 - A, SiO 2 , fig 1 7A, text [0042]) &[ 0025]) over the metal layer; forming a second etch stop layer (220-B, SiO 2 , fig 17A, text [0042]) on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer; forming a second dielectric layer (222, fig 17A, text [0026 ]) on the second etch stop layer; and forming a second conductive feature (226, fig 17A) in the second dielectric layer through the second etch stop layer, the first etch stop layer, and the metal layer. ► With respect to claim 2, Hsueh et al discloses forminq a first barrier layer (212, fig 17A) between the one or more first conductive features and the first dielectric layer. ► With respect to claim 3, Hsueh et al discloses wherein the pre-layer is extended to cover on exposed surfaces of the metal layer, the first barrier layer, and the first dielectric layer ► With respect to claim 8 , Hsueh et al (fig 17A) discloses the second conductive feature is disposed through the second etch stop layer, the first etch stop layer, the pre-layer, and the metal layer. ► With respect to claim 9 , Hsueh et al discloses forming a second barrier layer (230, text [0028]) , wherein the second barrier layer extends between and in contact with the second conductive feature, the second dielectric layer, the second etch stop layer, the first etch stop layer, and the pre-layer. 2. Claims 11, 14-16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al [ US 2022/0285210 ] ► With respect to claim 11 , Lin et al (figs 1-6, text [0001] -[ 0081]) discloses the claimed method for forming a semiconductor device structure, comprising: forming one or more first conductive features (106A, fig 1A , text[ 0017]- [0019] ) in a first dielectric layer (102) ; forming a metal layer (106 B , fig 1A , text [0019] ) on each of the one or more first conductive features; selectively forming a pre-layer (112A, fig 1B) on the metal layers; covering exposed surfaces of the pre-layer with a first etch stop (112B) so that a portion of the first etch stop layer is in contact with the first dielectric layer; and forming a second etch stop layer (114, fig 3B) on the first etch stop layer. ► With respect to claim 14, Lin et al discloses forming a first barrier layer (108 , fig 1A, text [0021]) contact with a sidewall surface of each first conductive feature. ► With respect to claim 15, Lin et al (fig 1A) discloses the metal layer is formed to cover a top of the first barrier layer. ► With respect to claim 1 6 , Lin et al (fig 1B) discloses a portion of the pre-layer is in contact with a top of the first barrier layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al [US 2022/0285210] in view of Hsueh et al [US 2021/0982920] ► With respect to claim 17, the claimed range of nitrogen contain in the pre-layer would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). ► With respect to claim 1 8 , Lin et al ( fig 3B) substantially discloses the claimed method for forming semiconductor structure comprising forming a second dielectric layer (120) on the second etch stop layer; forming a second conductive feature (142) in the second dielectric layer through the second etch stop layer, the first etch stop layer, and the metal layer ; and forming a second barrier layer (144) between the second dielectric layer and the second conductive feature. Lin et al does not expressly teach the second conductive feature through the metal layer and the second barrier is in contact with the first conductive feature. However, Hsueh et al (fig 17A) teaches the second conductive feature (226’) through the metal layer and the second barrier (230) is in contact with the first conductive feature. Therefore, it would have been obvious for those skilled in the art to modify process Lin et al by forming the second conductive feature and the second barrier layer as being claimed, per taught by Hsueh et al to provide semiconductor device with improved interconnection performance. Allowable Subject Matter Claims 21-22 are allowed. Claims 4-7, 12-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT THANHHA S PHAM whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1696 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT William Partridge can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-1402 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THANHHA S PHAM/ Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jun 09, 2023
Application Filed
Dec 13, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
89%
With Interview (+3.8%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 872 resolved cases by this examiner. Grant probability derived from career allow rate.

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