DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 7/22/2026 is acknowledged.
Applicant amended claims 1, 6, and 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8, 10-12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2009/0230479) (hereafter Hsu), in view of Hamaguchi (US 2006/0131657) (hereafter Hamaguchi).
Regarding claim 1, Hsu discloses a transistor structure comprising
a semiconductor substrate 20 (Fig. 11, paragraph 0021) with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11);
a gate region (124, 126, 132, 134, 143, 174, and 162 in Fig. 11) with a first gate conductive portion (lower portion of 134 in Fig. 11) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive portion (upper center portion of 134 in Fig. 11) over the first gate conductive portion (lower portion of 134 in Fig. 11);
wherein the first gate conductive portion (lower portion of 134 in Fig. 11) and the second gate conductive portion (upper center portion of 134 in Fig. 11) both are made of semiconductor material (see paragraph 0026, wherein “polysilicon layer”);
a spacer 143 (Fig. 11, paragraph 0027) covering a sidewall of the gate region (124, 126, 132, 134, 143, 174, and 162 in Fig. 11);
a conductive region (144, 142, and 146 in Fig. 11, paragraph 0027);
wherein the second gate conductive portion (upper center portion of 134 in Fig. 11) is directly connected to the first gate conductive portion (lower portion of 134 in Fig. 11) and extended upward from the first gate conductive portion (lower portion of 134 in Fig. 11); a lateral length of the first gate conductive portion (lower portion of 134 in Fig. 11) is greater than that of the second gate conductive portion (upper center portion of 134 in Fig. 11); and atop surface of the first gate conductive portion (lower portion of 134 in Fig. 11) is not higher than a bottom surface of the second gate conductive portion (upper center portion of 134 in Fig. 11).
Hsu does not disclose a trench formed below the semiconductor surface of the semiconductor substrate;
an isolation region in the trench; and
a conductive region positioned on the isolation region and disposed in the trench.
Hamaguchi discloses a trench (element number is not shown in Fig. 1 but see 45 in Fig. 2B, paragraph 0038) formed below the semiconductor surface (top surface of 41 in Fig. 1) of the semiconductor substrate (40 and 41 in Fig. 1);
an isolation region 17 (Fig. 1, paragraph 0030) in the trench; and
a conductive region 27 (Fig. 1, paragraph 0030) positioned on the isolation region 17 (Fig. 1) and disposed in the trench.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu to form a trench formed below the semiconductor surface of the semiconductor substrate; an isolation region in the trench; and a conductive region positioned on the isolation region and disposed in the trench, as taught by Hamaguchi, in order to reduce (Hamaguchi, paragraph 0033) the junction capacitance and the leak current of the source/drain region 27 (Hamaguchi, Fig. 1, paragraph 0033).
Regarding claim 3, Hsu in view of Hamaguchi discloses the transistor structure according to claim 1, however Hsu does not disclose the conductive region is independent from the semiconductor substrate.
Hamaguchi discloses the conductive region 27 (Fig. 1, paragraph 0030) is independent from the semiconductor substrate (40 and 41 in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu to form the conductive region is independent from the semiconductor substrate, as taught by Hamaguchi, in order to reduce (Hamaguchi, paragraph 0033) the junction capacitance and the leak current of the source/drain region 27 (Hamaguchi, Fig. 1, paragraph 0033).
Regarding claim 4, Hsu further discloses the transistor structure according to claim 3, wherein the transistor structure is a planar NMOS transistor 102 (Fig. 11, paragraph 0027), the conductive region (144, 142, and 146 in Fig. 11) comprises an N type lightly-doped drain (LDD) region 142 (Fig. 11, paragraph 0027) and an N type heavily doped region 144 (Fig. 11, paragraph 0027) contacting with the N type LDD region 142 (Fig. 11).
Regarding claim 5, Hsu further discloses the transistor structure according to claim 4, wherein a top surface of the N type LDD region 142 (Fig. 11) is substantially covered by the spacer 143 (Fig. 11).
Regarding claim 6, Hsu discloses a transistor structure comprising
a semiconductor substrate 20 (Fig. 11, paragraph 0021) with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11);
a gate region (124, 126, 132, 134, 143, 174, and 162 in Fig. 11) with a first gate conductive portion (lower portion of 134 in Fig. 11) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive portion (upper center portion of 134 in Fig. 11) over the first conductive portion (lower portion of 134 in Fig. 11), wherein the first gate conductive portion (lower portion of 134 in Fig. 11) and the second gate conductive portion (upper center portion of 134 in Fig. 11) both are made of semiconductor material (see paragraph 0026, wherein “polysilicon layer”);
a spacer 143 (Fig. 11, paragraph 0027) covering a sidewall of the gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11);
a conductive region (144, 142, and 146 in Fig. 11, paragraph 0027);
wherein a lateral length of the first gate conductive portion (lower portion of 134 in Fig. 11) is greater than that of the second gate conductive portion (upper center portion of 134 in Fig. 11); a top surface of the first gate conductive portion (lower portion of 134 in Fig. 11) is lower than a top surface of the second gate conductive portion (upper center portion of 134 in Fig. 11).
Hsu does not disclose a trench formed below the semiconductor surface of the semiconductor substrate;
an isolation region in the trench;
a conductive region positioned on the isolation region and disposed in the trench; and
wherein the isolation region further comprises a bottom layer, a vertical layer and a filling dielectric region on the bottom layer, and a top surface of the vertical layer is aligned or substantially aligned with that of the filling dielectric region.
Hamaguchi discloses a trench (element number is not shown in Fig. 1 but see 45 in Fig. 2B, paragraph 0038) formed below the semiconductor surface (top surface of 41 in Fig. 1) of the semiconductor substrate (40 and 41 in Fig. 1);
an isolation region 17 (Fig. 1, paragraph 0030) in the trench;
a conductive region 27 (Fig. 1, paragraph 0030) positioned on the isolation region 17 (Fig. 1) and disposed in the trench; and
wherein the isolation region 17 (Fig. 1) further comprises a bottom layer (bottom horizontal portion of 17 in Fig. 1), a vertical layer (vertical portion of 17 contacting 27 in Fig. 1) and a filling dielectric region (upper horizontal portion of 17 in Fig. 1) on the bottom layer (bottom horizontal portion of 17 in Fig. 1), and a top surface (top surface of 17 contacting 21 in Fig. 1) of the vertical layer (vertical portion of 17 contacting 27 in Fig. 1) is aligned (see Fig. 1, wherein top surface of 17 contacting 21 is vertically aligned with the upper horizontal portion of 17) or substantially aligned with that of the filling dielectric region (upper horizontal portion of 17 in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu to form a trench formed below the semiconductor surface of the semiconductor substrate; an isolation region in the trench; a conductive region positioned on the isolation region and disposed in the trench; and wherein the isolation region further comprises a bottom layer, a vertical layer and a filling dielectric region on the bottom layer, and a top surface of the vertical layer is aligned or substantially aligned with that of the filling dielectric region, as taught by Hamaguchi, in order to reduce (Hamaguchi, paragraph 0033) the junction capacitance and the leak current of the source/drain region 27 (Hamaguchi, Fig. 1, paragraph 0033).
Regarding claim 8, Hsu in view of Hamaguchi discloses the transistor structure according to claim 6, however Hsu does not disclose the N type LDD region is on the vertical layer and the N type heavily doped region is on the filling dielectric region.
Hamaguchi discloses the N type LDD region 21 (Fig. 1, paragraph 0043) is on the vertical layer (vertical portion of 17 contacting 27 in Fig. 1) and the N type heavily doped region 27 (Fig. 1, paragraph 0046) is on the filling dielectric region (upper horizontal portion of 17 in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu to form the N type LDD region is on the vertical layer and the N type heavily doped region is on the filling dielectric region, as taught by Hamaguchi, in order to reduce (Hamaguchi, paragraph 0033) the junction capacitance and the leak current of the source/drain region 27 (Hamaguchi, Fig. 1, paragraph 0033).
Regarding claim 10, Hsu further discloses the transistor structure according to claim 1, further comprising a shallow trench isolation (STI) region 18 (Fig. 11, paragraph 0021) below the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and an extending dielectric layer 140 (Fig. 11, paragraph 0027) above the STI region 18 (Fig. 11), wherein the extending dielectric layer 140 (Fig. 11) includes a vertical portion (portion of 140 contacting lateral surface of 146 in Fig. 11), and a top surface of the vertical portion (portion of 140 contacting lateral surface of 146 in Fig. 11) is higher than the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11).
Regarding claim 11, Hsu further discloses the transistor structure according to claim 10, wherein the conductive region (144, 142, and 146 in Fig. 11) is confined by the vertical portion (portion of 140 contacting lateral surface of 146 in Fig. 11) of the extending dielectric layer 140 (Fig. 11).
Regarding claim 12, Hsu discloses a transistor structure comprising:
a semiconductor substrate 20 (Fig. 11, paragraph 0021) with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11);
a gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11) with a first gate conductive portion (lower center portion of 134 in Fig. 11) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive portion (upper portion of 134 in Fig. 11) over the first gate conductive portion (lower center portion of 134 in Fig. 11), wherein the second gate conductive portion (upper portion of 134 in Fig. 11) has uniform lateral length;
a channel region (region of 20 between 144 in Fig. 11) being under the gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11);
a drain region (right 144 in Fig. 11, paragraph 0027); and
a source region (left 144 in Fig. 11, paragraph 0027);
wherein the second gate conductive portion (upper portion of 134 in Fig. 11) is directly connected to the first gate conductive portion (lower center portion of 134 in Fig. 11) and extended upward from the first gate conductive portion (lower center portion of 134 in Fig. 11); a lateral length of the first gate conductive portion (lower center portion of 134 in Fig. 11) is different from that of the second gate conductive portion (upper portion of 134 in Fig. 11); and a top surface of the first gate conductive portion (lower center portion of 134 in Fig. 11) is not higher than a bottom surface of the second gate conductive portion (upper portion of 134 in Fig. 11).
Hsu does not disclose a first trench and a second trench, both formed below the semiconductor surface;
a first isolation region in the first trench;
a second isolation region in the second trench;
a drain region with a first doping type on the first isolation region; and
a source region with the first doping type on the second isolation region.
Hamaguchi discloses a first trench (element number is not shown in Fig. 1 but see right 45 in Fig. 2B, paragraph 0038) and a second trench (element number is not shown in Fig. 1 but see left 45 in Fig. 2B, paragraph 0038), both formed below the semiconductor surface (40 and 41 in Fig. 2B, paragraph 0029);
a first isolation region (right 17 of 43 in Fig. 1, paragraph 0030) in the first trench (element number is not shown in Fig. 1 but see right 45 in Fig. 2B);
a second isolation region (left 17 of 43 in Fig. 1, paragraph 0030) in the second trench (element number is not shown in Fig. 1 but see left 45 in Fig. 2B);
a drain region (right 27 in Fig. 1, paragraph 0030) with a first doping type on the first isolation region (right 17 of 43 in Fig. 1); and
a source region (left 27 in Fig. 1, paragraph 0030) with the first doping type on the second isolation region (left 17 of 43 in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu to form a first trench and a second trench, both formed below the semiconductor surface; a first isolation region in the first trench; a second isolation region in the second trench; a drain region with a first doping type on the first isolation region; and a source region with the first doping type on the second isolation region, as taught by Hamaguchi, in order to reduce (Hamaguchi, paragraph 0033) the junction capacitance and the leak current of the source/drain region 27 (Hamaguchi, Fig. 1, paragraph 0033).
Regarding claim 14, Hsu further discloses the transistor structure according to claim 12, further comprising a STI region 18 (Fig. 11, paragraph 0021) below the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and an extending dielectric layer 140 (Fig. 11, paragraph 0027) above the STI region 18 (Fig. 11), wherein the extending dielectric layer 140 (Fig. 11) includes a vertical portion (vertical portion of 140 in Fig. 11) surrounding the active region 20 (Fig. 11), and a top surface of the vertical portion (vertical portion of 140 in Fig. 11) is higher than the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11).
Regarding claim 15, Hsu further discloses the transistor structure according to claim 14, wherein the drain region (right 144 in Fig. 11) and the source region (left 144 in Fig. 11) are confined by the vertical portion of the extending dielectric layer (vertical portion of 140 in Fig. 11).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Hamaguchi as applied to claim 8 above, and further in view of Lenoble et al. (US 2004/0262682) (hereafter Lenoble) and Yang et al. (US 2010/0289093) (hereafter Yang).
Regarding claim 9, Hsu in view of Hamaguchi discloses the transistor structure according to claim 8, however Hsu and Hamaguchi do not disclose a vertical thickness of the N type LDD region is less than 20 nm, and a lateral width of the N type LDD region is between 10~30 nm.
Lenoble discloses a vertical thickness of the N type LDD region 8 (Fig. 1D, paragraph 0012, wherein “at most 20 nm”) is less than 20nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu in view of Hamaguchi to form a vertical thickness of the N type LDD region is less than 20 nm, as taught by Lenoble, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Hsu, Hamaguchi, and Lenoble do not disclose a lateral width of the N type LDD region is between 10~30 nm.
Yang disclose a lateral width L1 (Fig. 4C, paragraph 0076, wherein “within a range of 50 angstroms to 150 angstroms”) of the N type LDD region 412a (Fig. 4C, paragraph 0076) is between 10~30 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hsu in view of Hamaguchi and Lenoble to form a lateral width of the N type LDD region is between 10~30 nm, as taught by Yang, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Allowable Subject Matter
1. Claims 2, 7, 13, 16, and 18-22 are allowed. The following is an examiner’s statement of reasons for allowance: a prior art, Hamaguchi (US 2006/0131657), discloses the isolation region 17 (Fig. 1, paragraph 0030) includes a vertical layer (vertical portion of 17 in Fig. 1) and a bottom layer (horizontal portion of 17 in Fig. 1); an edge of the vertical layer (vertical portion of 17 in Fig. 1) is underneath the spacer 26 (Fig. 1, paragraph 0031) but fails to disclose a gap between the edge of the vertical layer and an edge of the first gate conductive portion of the gate region is less than 3nm. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a transistor structure comprising a gap between the edge of the vertical layer and an edge of the first gate conductive portion of the gate region is less than 3 nm in combination with other elements of claim 2.
In addition, a prior art, Hamaguchi (US 2006/0131657), discloses the isolation region 17 (Fig. 1) further comprises a bottom layer (bottom horizontal portion of 17 in Fig. 1), a vertical layer (vertical portion of 17 contacting 27 in Fig. 1) and a filling dielectric region (upper horizontal portion of 17 in Fig. 1) on the bottom layer (bottom horizontal portion of 17 in Fig. 1), and a top surface (top surface of 17 contacting 21 in Fig. 1) of the vertical layer (vertical portion of 17 contacting 27 in Fig. 1) is aligned (see Fig. 1, wherein top surface of 17 contacting 21 is vertically aligned with the upper horizontal portion of 17) or substantially aligned with that of the filling dielectric region (upper horizontal portion of 17 in Fig. 1) but fails to disclose the vertical layer and the bottom layer of the isolation region are made of oxide, and the filling dielectric region is made of a spin-on-dopant (SOD) layer. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a transistor structure comprising the vertical layer and the bottom layer of the isolation region are made of oxide, and the filling dielectric region is made of a spin-on-dopant (SOD) layer in combination with other elements of claim 7.
Moreover, a prior art, Hamaguchi (US 2006/0131657), discloses a distance between an edge (right side surface of right 17 of 43 in Fig. 1) of the first isolation region (right 17 of 43 in Fig. 1) and an edge (left side surface of left 17 of 43 in Fig. 1) of the second isolation region (left 17 of 43 in Fig. 1) is greater than the lateral length of the first gate conductive portion 13a (Fig. 1) but fails to disclose the distance between the edge of the first isolation region and the edge of the second isolation region is greater than the length of the lateral length of the first gate conductive portion around 2-6 nm. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a transistor structure comprising the isolation region further comprises the distance between the edge of the first isolation region and the edge of the second isolation region is greater than the length of the lateral length of the first gate conductive portion around 2-6 nm in combination with other elements of claim 13.
Furthermore, a closest prior art, Hamaguchi (US 2006/0131657), discloses a second gate conductive 162 (Fig. 11, paragraph 0035) portioned over the first gate conductive portion 134 (Fig. 11); a first spacer (left 143 in Fig. 11, paragraph 0027) and a second spacer (right 143 in Fig. 11, paragraph 0027); and the first spacer (left 143 in Fig. 11) contacts sidewalls of the first gate conductive portion (132 and 134 in Fig. 11 in Fig. 11) but fails to disclose the second spacer contacts sidewalls of the second gate conductive portion rather than the first gate conductive portion, and the first spacer contacts sidewalls of the first gate conductive portion. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a transistor structure comprising the second spacer contacts sidewalls of the second gate conductive portion rather than the first gate conductive portion, and the first spacer contacts sidewalls of the first gate conductive portion in combination with other elements of claim 16.
A closest prior art, Hsu et al. (US 2009/0230479), discloses a transistor structure comprising a semiconductor substrate 20 (Fig. 11, paragraph 0021) with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11); a gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11) with a first gate conductive portion (134 and 160 in Fig. 11) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive portion (174, 162, and 72 in Fig. 11, paragraph 0035) over the first conductive portion (134 and 160 in Fig. 11); a spacer 143 (Fig. 11, paragraph 0027) covering a sidewall of the gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11); a conductive region (144, 142, and 146 in Fig. 11, paragraph 0027); wherein the second gate conductive portion (174, 162, and 72 in Fig. 11) is directly connected to the first gate conductive portion (134 and 160 in Fig. 11) and extended upward from the first gate conductive portion (134 and 160 in Fig. 11); a lateral length of the first gate conductive portion (134 and 160 in Fig. 11) is greater (see Fig. 11, wherein the lateral length of 134 is greater than the lateral length of 72) than that of the second gate conductive portion (174, 162, and 72 in Fig. 11); and atop surface of the first gate conductive portion (134 and 160 in Fig. 11) is not higher than a bottom surface of the second gate conductive portion (174, 162, and 72 in Fig. 11) but fails to teach a trench formed below the semiconductor surface of the semiconductor substrate; an isolation region in the trench; a conductive region positioned on the isolation region and disposed in the trench; wherein the isolation region includes a vertical layer and a bottom layer; an edge of the vertical layer is underneath the spacer; and a gap between the edge of the vertical layer and an edge of the first gate conductive portion of the gate region is less than 3 nm as the context of claim 2.
In addition, a closest prior art, Hsu et al. (US 2009/0230479), discloses a transistor structure comprising a semiconductor substrate 20 (Fig. 11, paragraph 0021) with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11); a gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11) with a first gate conductive portion (134 and 160 in Fig. 11) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive portion (174, 162, and 72 in Fig. 11, paragraph 0035) over the first conductive portion (134 and 160 in Fig. 11); a spacer 143 (Fig. 11, paragraph 0027) covering a sidewall of the gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11); a conductive region (144, 142, and 146 in Fig. 11, paragraph 0027); wherein the second gate conductive portion (174, 162, and 72 in Fig. 11) is directly connected to the first gate conductive portion (134 and 160 in Fig. 11) and extended upward from the first gate conductive portion (134 and 160 in Fig. 11); a lateral length of the first gate conductive portion (134 and 160 in Fig. 11) is greater (see Fig. 11, wherein the lateral length of 134 is greater than the lateral length of 72) than that of the second gate conductive portion (174, 162, and 72 in Fig. 11); and atop surface of the first gate conductive portion (134 and 160 in Fig. 11) is not higher than a bottom surface of the second gate conductive portion (174, 162, and 72 in Fig. 11) but fails to teach a trench formed below the semiconductor surface of the semiconductor substrate; an isolation region in the trench; a conductive region positioned on the isolation region and disposed in the trench; wherein the vertical layer and the bottom layer of the isolation region are made of oxide, and the filling dielectric region is made of a spin-on-dopant (SOD) layer as the context of claim 7.
Moreover, a closest prior art, Hsu et al. (US 2009/0230479), discloses a transistor structure comprising: a semiconductor substrate 20 (Fig. 11, paragraph 0021) with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11); a gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11) with a first gate conductive portion (134 and 160 in Fig. 11) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive portion 162 (Fig. 11, paragraph 0035) over the first gate conductive portion (134 and 160 in Fig. 11); a channel region (region of 20 between 144 in Fig. 11) being under the gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11); a drain region (right 144 in Fig. 11, paragraph 0027); and a source region (left 144 in Fig. 11, paragraph 0027); wherein the second gate conductive portion (174, 162, and 72 in Fig. 11) is directly connected to the first gate conductive portion (134 and 160 in Fig. 11) and extended upward from the first gate conductive portion (134 and 160 in Fig. 11); a lateral length of the first gate conductive portion (134 and 160 in Fig. 11) is different (see Fig. 11, wherein the lateral length of 134 is greater than the lateral length of 72) from that of the second gate conductive portion (174, 162, and 72 in Fig. 11); and a top surface of the first gate conductive portion (134 and 160 in Fig. 11) is not higher than a bottom surface of the second gate conductive portion (174, 162, and 72 in Fig. 11) but fails to teach a first trench and a second trench, both formed below the semiconductor surface; a first isolation region in the first trench; a second isolation region in the second trench; a drain region with a first doping type on the first isolation region; a source region with the first doping type on the second isolation region; and wherein the distance between the edge of the first isolation region and the edge of the second isolation region is greater than the length of the lateral length of the first gate conductive portion around 2~6 nm as the context of claim 13.
Furthermore, a closest prior art, Hsu et al. (US 2009/0230479), discloses a transistor structure comprising a semiconductor substrate 20 (Fig. 11, paragraph 0021), with an active region 20 (Fig. 11) and with a semiconductor surface (top surface of 20 in Fig. 11); and a gate region (124, 126, 132, 134, 143, 174, 162, and 72 in Fig. 11) with a first gate conductive portion (132 and 134 in Fig. 11, paragraph 0026) over the semiconductor surface (top surface of 20 in Fig. 11) of the semiconductor substrate 20 (Fig. 11) and a second gate conductive 162 (Fig. 11, paragraph 0035) portioned over the first gate conductive portion (132 and 134 in Fig. 11 in Fig. 11); and wherein a lateral length of the first gate conductive portion (132 and 134 in Fig. 11 in Fig. 11) is greater than that of the second gate conductive portion 162 (Fig. 11) but fails to teach a first spacer and a second spacer, wherein the second spacer contacts sidewalls of the second gate conductive portion rather than the first gate conductive portion, and the first spacer contacts sidewalls of the first gate conductive portion as the context of claim 16. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 18-22 depend on claim 16.
Response to Arguments
1. Applicant's arguments filed 7/22/2026 have been fully considered.
2. The applicant argues (REMARKS, Bridging paragraph from page 13 to page 14) that “"Hsu" fails to teach the features of first gate conductive portion and the second gate conductive portion both are made of semiconductor material...a lateral length of the first gate conductive portion is greater than [different from] that of the second gate conductive portion; a top surface of the first gate conductive portion is lower than a bottom surface of the second gate conductive portion" as recited in the amended independent claims 1, 6 and 12 of the present application.” However, Hsu et al. (US 2009/0230479) disclose the first gate conductive portion (lower portion of 134 in Fig. 11) and the second gate conductive portion (upper center portion of 134 in Fig. 11) both are made of semiconductor material (see paragraph 0026, wherein “polysilicon layer”); a spacer 143 (Fig. 11, paragraph 0027) covering a sidewall of the gate region (124, 126, 132, 134, 143, 174, and 162 in Fig. 11); a conductive region (144, 142, and 146 in Fig. 11, paragraph 0027); wherein the second gate conductive portion (upper center portion of 134 in Fig. 11) is directly connected to the first gate conductive portion (lower portion of 134 in Fig. 11) and extended upward from the first gate conductive portion (lower portion of 134 in Fig. 11); a lateral length of the first gate conductive portion (lower portion of 134 in Fig. 11) is greater than that of the second gate conductive portion (upper center portion of 134 in Fig. 11); and atop surface of the first gate conductive portion (lower portion of 134 in Fig. 11) is not higher than a bottom surface of the second gate conductive portion (upper center portion of 134 in Fig. 11).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
