Technology area: Semiconductors, Circuits & Optics
7 pending office actions • 5 art units • 6 examiners • 0 of 7 (0%) have an AI response strategy ready • 11 patents granted in the last 365 days
Invention And Collaboration Laboratory Pte. Ltd. has 6 pending office actions in Semiconductors, Circuits & Optics. The matters involve 6 distinct examiners across 5 distinct art units. The examiner distribution is broader than the art-unit distribution, indicating that at least one art unit handles more than one matter.
TRAN, ANTHAN is the busiest examiner, with 1 pending matter. No examiner has a larger listed concentration, so portfolio oversight should account for all six examiner relationships. The repeated art-unit assignment creates an opportunity to compare examination positions within the same unit while preserving matter-specific response strategies.
A centralized record of claim amendments, cited references, and interview outcomes can help counsel identify recurring semiconductor issues. It can also prevent assumptions that a position accepted in one file will receive the same treatment in another examiner’s case.
Based on the USPTO statutory response window for each pending office action. 4 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 4 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 2 (29%) |
| §102 only | 2 (29%) |
| Multi-statute (no §101) | 3 (43%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| KOO, LAMONT B | 2 | 80.6% | +5.2% |
| TRAN, ANTHAN | 1 | 83.0% | +2.4% |
| GRAY, AARON J | 1 | 82.3% | +29.8% |
| PAGE, STEVEN MITCHELL CHR | 1 | 83.7% | +8.8% |
| OH, JIYOUNG | 1 | 76.1% | +15.8% |
| MIHALIOV, DMITRI | 1 | 74.2% | +33.3% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18494783 | SEMICONDUCTOR DEVICE STRUCTURE WITH VERTICAL TRANSISTOR OVER UNDERGROUND BIT LINE | KOO, LAMONT B | 50d overdue |
| 18770651 | DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUIT | TRAN, ANTHAN | 32d overdue |
| 18208388 | TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME | KOO, LAMONT B | 61d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18223560 | MEMORY CELL STRUCTURE | PAGE, STEVEN MITCHELL CHR | 2d overdue |
| 18518581 | SEMICONDUCTOR TRANSISTOR WITH PRECISE GEOMETRIES AND RELATED MANUFACTURE METHOD THEREOF | GRAY, AARON J | — |
| 17993982 | TRANSISTOR STRUCTURE | OH, JIYOUNG | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18518581 | SEMICONDUCTOR TRANSISTOR WITH PRECISE GEOMETRIES AND RELATED MANUFACTURE METHOD THEREOF | GRAY, AARON J | — |
| 17993982 | TRANSISTOR STRUCTURE | OH, JIYOUNG | — |
| 17898664 | STANDARD CELL STRUCTURE | MIHALIOV, DMITRI | — |
| Art Unit | Apps |
|---|---|
| 2813 | 2 |
| 2812 | 2 |
| 2825 | 1 |
| 2897 | 1 |
| 2818 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18770651 | DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUIT | TRAN, ANTHAN | 2825 | §102 | Non-Final OA | 32d overdue | Pending | Jul 12, 2024 |
| 18518581 | SEMICONDUCTOR TRANSISTOR WITH PRECISE GEOMETRIES AND RELATED MANUFACTURE METHOD THEREOF | GRAY, AARON J | 2897 | §102§103 | Non-Final OA | — | Pending | Nov 23, 2023 |
| 18494783 | SEMICONDUCTOR DEVICE STRUCTURE WITH VERTICAL TRANSISTOR OVER UNDERGROUND BIT LINE | KOO, LAMONT B | 2813 | §102 | Non-Final OA | 50d overdue | Pending | Oct 26, 2023 |
| 18223560 | MEMORY CELL STRUCTURE | PAGE, STEVEN MITCHELL CHR | 2812 | §102§103 | Final Rejection | 2d overdue | Pending | Jul 19, 2023 |
| 18208388 | TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME | KOO, LAMONT B | 2813 | §103 | Final Rejection | 61d | Pending | Jun 12, 2023 |
| 17993982 | TRANSISTOR STRUCTURE | OH, JIYOUNG | 2818 | §103§112 | Non-Final OA | — | Pending | Nov 24, 2022 |
| 17898664 | STANDARD CELL STRUCTURE | MIHALIOV, DMITRI | 2812 | §103 | Non-Final OA | — | Pending | Aug 30, 2022 |
IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.
Start Free TrialInvention And Collaboration Laboratory Pte. Ltd. has 7 pending office actions as of October 2026, spread across 5 art units and 6 examiners.
Lamont B Koo has the most, with 2 of Invention And Collaboration Laboratory Pte. Ltd.'s pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
