Attorney Docket Number: 22520.63
Filing Date: 06/13/2023
Claimed Priority Date: none
Inventors: Dixit et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 10/20/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election with traverse of Invention I, reading on a semiconductor device, and without traverse of Species 3, reading on figure 1 as constructed through figures 2A-2J, in the reply filed on 10/20/2025, is acknowledged.
The traversal is on the grounds that because claim 1 (i.e., the group-I invention) has been amended to include the wet etching previously only recited in claim 11 (i.e., the group-II invention), execution of the recited method of the group-II invention would likely result in the structure of the group-I invention, and thus it is likely that any art found relevant to the patentability of the group-II invention would also be applicable to the group-I invention and vice versa. This is not found persuasive.
As put forth in paragraph 4 of the restriction requirement mailed on 08/19/2025, the inventions are drawn to separate fields of search, showing that each invention has attained recognition in the semiconductor art as a separate field of inventive effort. As such, examining both groups of claims would most likely require different searching fields, as evinced by their separate classification, thereby creating a burden on the examiner. For an additional example to illustrate this point, the group-I invention is further classifiable and searchable in class H10D 30/4732 and the group-II invention is further classifiable and searchable in class H01L 21/022, again demonstrating that each invention has attained recognition in the semiconductor art as a separate field of inventive effort, thus imposing a serious search and/or examination burden on the examiner.
Furthermore, as put forth in paragraph 5 of the restriction requirement, the inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). Even considering the amendments to the group-I and group-II inventions, unpatentability of the group-I invention would not necessarily imply unpatentability of the group-II invention since the device of the group-I invention could be made by processes materially different than those of the group-II invention. For example, instead of the step of claim 11 reciting “etching contact openings through the passivation layer for a source contact and a drain contact”, the source contact and drain contact contact openings of claim 1 could be made by performing a laser ablation process or by depositing a printed passivation layer made with openings for a source contact and drain contact such that no etching is required. Furthermore, instead of the step of claim 11 reciting “etching the blanket p-GaN layer to define p-GaN gate regions”, the device of claim 1 could be made by forming without forming any blanket p-GaN layer or p-GaN gate regions at all. Accordingly, alternative methods, different from the one claimed in the group-II, may be used to make the device in the claims of the group-II invention. As such, examining both groups of claims would most likely require different searching fields, as evinced by their separate classification, thereby creating a burden on the examiner.
For all of the above reasons, the requirement is still deemed proper and is therefore, made final.
The applicant indicated that claims 1-20 read on the elected invention and species. Claims 1-10 and 19-20, however, read on a non-elected invention (i.e., the group-I invention) of the claimed invention. Accordingly, claims 1-10 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention and/or species, there being no allowable generic or linking claim.
Drawings
Quotes from the specification are from the published application US 2024/0421196.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims. No new matter should be entered.
“etching the blanket p-GaN layer to define p-GaN gate regions”, as recited in claim 11
“providing a passivation layer covering the p-GaN gate regions”, as recited in claim 11
“etching gate contact openings through the passivation layers”, as recited in claim 11
“the etching of the gate contact openings comprising etching gate contact openings through the first and second passivation layers to the p-GaN gate regions”, as recited in claim 17
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "228" and "228-2" have both been used to designate a gate metal field plate with an extended slanted profile in figure 3 (see par.0071/ll.8-10).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference signs mentioned in the description: 300-4, 288-2.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because figures 1 and 3 include the following reference characters not mentioned in the description: Dielectric 2, Dielectric 4, Conductive vias 1, Conductive vias 2.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
The claims are objected to because of the following informalities:
In claim 16, lines 1-2, “depositing and patterning gate metal to form gate contact” should read “depositing and patterning gate metal to form the gate contact”
Appropriate correction is required. No new matter should be added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11-18 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 11 recites the limitation “etching the blanket p-GaN layer to define p-GaN gate regions”. No “blanket p-GaN layer” has been previously recited in the claim. As such, there is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “providing a passivation layer covering the p-GaN gate regions”. As discussed in paragraph 18 above, no “blanket p-GaN layer” has been previously recited in the claim, and thus the “p-GaN gate regions” recited in the claim have no antecedent basis. Accordingly, the limitation “providing a passivation layer covering the p-GaN gate regions” has insufficient antecedent basis.
Claim 11 recites the limitation “etching gate contact openings through the passivation layers”, indicating a plurality of passivation layers. No “passivation layers” or plurality of “passivation layers” has been previously recited in the claim. As such, there is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “a bottom of the third dielectric layer”. No “third dielectric layer” has been previously recited in the claim. As such, there is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “a top of the third dielectric layer”. No “third dielectric layer” has been previously recited in the claim. As such, there is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation “the dielectric passivation layer”. Although separate instances of “a dielectric layer” and “a passivation layer” are recited in parental claim 11, no combined “dielectric passivation layer” has been previously recited in the claim or in any parental claim. As such, there is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation “an electric field under the slated gate field plate between the gate contact and the drain contact”. Two distinct gate and drain contacts are formed in parental claim 11, a gate and a drain contact through a passivation layer and a gate and a drain contact through a dielectric layer. As such, this limitation in the claims is indefinite as it is unclear to which one of the two gate and two drain contacts the claim is specifically referring.
Claim 17 recites the limitation “to the p-GaN gate regions”. No “p-GaN gate regions” have been previously sufficiently recited in the claim or in any parental claim (see paragraphs 18-19 above). As such, there is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation “the GaN semiconductor being an enhancement-mode GaN semiconductor power transistor”. No single “GaN semiconductor” has been previously recited in the claim or in any parental claim. As such, there is insufficient antecedent basis for this limitation in the claim.
Claims 12-18 depend from claim 11 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 13-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Khalil (US 2022/0208975) in view of Lei (US 2022/0157977), Kuo (US 2023/0361204), and Glass (US 2022/0093790).
Regarding claim 1, Khalil (see, e.g., figs. 1, 3-8, 9A, and 10A) shows most aspects of the instant invention, including a method 300 of fabricating a GaN semiconductor power transistor 100 comprising:
providing an epitaxial layer structure 102/104/106/108 comprising a semiconductor substrate 102, a buffer layer 104, a GaN semiconductor heterostructure 106/108 (see, e.g., pars.0021/ll.7 and 0022/ll.14-15) comprising a GaN channel layer 106 and an AlGaN barrier layer 108 providing a 2DEG active region 107 (see, e.g., par.0022/ll.7-11);
providing a passivation layer 130;
etching (see, e.g. par.0041/ll.7) contact openings 132, 134 through the passivation layer for a source contact 140 and a drain contact 145;
depositing and patterning ohmic contact metal (see, e.g., pars.0041/ll.3-4, 13, and 22-24 and 0043/ll.1-3) to form the source contact 140 and drain contact 145;
etching (see, e.g., par.0046/ll.5-6) a gate contact opening 136 through the passivation layer;
depositing and patterning gate metal (see, e.g., pars.0045/ll.6-10 and 0046/ll.12-13) to form a gate contact 150 and a gate metal field plate 160;
depositing a dielectric layer 170 overall (see, e.g., par.0030/ll.1-4);
performing a first etch process (see, e.g., par.0049) of the dielectric layer 170 to form contact openings 172, 178 for a source contact 185 and a drain contact 186;
performing a second patterning process (see, e.g., par.0048/ll.1-7) of the dielectric layer 170 to form a slanted opening (unlabeled opening/dip in 170 laterally between the horizontal centers of 150 and 160) for a slanted gate field plate 180; and
depositing at least one layer of conductive metal (see, e.g., fig. 10A and par.0050) to fill the contact openings 172, 178 for the source contact 185 and drain contact 186 and to form the slanted gate field plate 180
Although Khalil shows most aspects of the instant invention, including the etching of one gate contact opening, Khalil fails to specify the creation of multiple gate contact openings. Lei, in the same field of endeavor, teaches a method for fabricating a GaN semiconductor power transistor 100, wherein a passivation/dielectric layer 220 (see, e.g., Lei: figs. 2A-4F and pars.0037/ll.13-15 and 0039/ll.7-9) is etched to create multiple gate contact openings 230, 232 such that a continuous gate contact 114 is formed filling the multiple contact openings (see, e.g., Lei: figs. 2A-4F and par.0040).
Lei is evidence showing that one of ordinary skill in the art would appreciate that having a GaN semiconductor power transistor with multiple etched gate contact openings would be equivalent to having a GaN semiconductor power transistor with a single etched gate contact opening, and that such differences would result in no unexpected changes in the performance of the device of Khalil. That is, the gate contact openings and structures of both Khalil and Lei would yield the predictable result of providing and establishing a suitable foundation and location for an electrically-conductive gate contact in a GaN semiconductor power transistor.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a GaN semiconductor power transistor comprising multiple etched gate contact openings, as taught by Lei, or a GaN semiconductor power transistor comprising a single etched gate contact opening, as taught by Khalil, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing and establishing a suitable foundation and location for an electrically-conductive gate contact for in GaN semiconductor power transistor. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, although Khalil teaches the depositing of a dielectric layer overall, Khalil fails to specify the composition of the dielectric layer. Additionally, although Khalil teaches that a second patterning process to create a slanted opening for a slanted gate field plate is performed in Khalil’s dielectric layer prior to the first etch process for forming source and drain contact openings in the dielectric layer (see, e.g., fig. 10A and pars.0048/ll.1-7 and 0049/ll.1-9, wherein a resist layer is placed atop an already-formed dielectric layer to create the openings 172, 178 for the source and drain contacts), Khalil fails to specify that an etch process comprising a wet etch is used to form this slanted opening in this second process.
Kuo, in the same field of endeavor, teaches that when a dielectric layer 104 is formed with a graded composition, for example, a composition wherein a bottom/lower level of the dielectric layer has a denser composition and a slower etch rate than a top/upper level of the dielectric layer, that in a wet-etch process material from the top/upper level of the dielectric layer is more easily removed than material from the bottom/lower level of the dielectric layer, aiding in the creation of a slanted opening shape (see, e.g., Kuo: fig. 1A and pars.0017/ll.1-33 and 0033). Kuo further teaches wet etching to be suitable for this material-removal process, and additionally asserts that wet etching allows removal of material from the dielectric layer while not substantially affecting the materials of nearby dielectric and doped structures (see, e.g., Kuo: par.0033/ll.26-33).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Khalil’s dielectric layer comprise a graded composition, as taught by Kuo, so as to have a dielectric layer more suitably composed for creating Khalil’s slanted opening. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art have Khalil’s second patterning process be a second etch process comprising a wet etch to form Khalil’s slanted opening, as taught by Kuo, as wet etching was explicitly taught to be suitable for use on a graded-composition dielectric layer to create a slanted opening shape, as taught by Kuo, and so as to protect the materials of Khalil’s nearby structures (e.g., Khalil’s passivation layer) from being substantially affected by the creation of Khalil’s slanted opening.
Additionally, although Khalil teaches that Khalil’s first etch process forms contact openings for a source contact and a drain contact, and that Khalil’s method further comprising a step of depositing at least one layer of conductive metal to fill the contact openings for the source contact and drain contact, Khalil fails to specify that Khalil’s first etch process forms contact openings for a gate contact and that at least one layer of conductive metal is deposited to fill the contact openings for the gate contact. Glass, in the same field of endeavor, teaches that having a metal gate contact structure 282 etched through a dielectric 280 in a GaN semiconductor power transistor 200 can enable an independent electrical connection to and control of a gate structure 208 (see, e.g., Glass: fig. 2 and pars.0062, 0106/ll.1-13, and 0114/ll.1-6). Glass further teaches that such an etching process to create contact openings for source, drain, and gate contacts enables elimination of the need for a lithography operation with exceedingly tight registration budget to generate a contact pattern (see, e.g., Glass: 0062 and 0106/ll.1-13).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Khalil’s first etch process include etching a contact opening for a gate contact in Khalil’s dielectric layer and depositing at least one layer of conductive metal to fill the contact opening for the gate contact, as taught by Glass, so as to create a contact structure enabling an independent electrical connection to and control of Khalil’s gate structure through a process enabling elimination of the need for a lithography operation with exceedingly tight registration budget to generate a contact pattern. With regards to the other language recited in claim 11, see the comments stated above in paragraphs 18-22.
Regarding claim 13, Khalil (see, e.g., pars.0032/ll.48-51 and 0050/ll.19) shows that the step of depositing at least one layer of conductive metal comprises depositing a single metal layer (e.g., a single metal layer is deposited to form source contact 185).
Regarding claim 14, Khalil (see, e.g., par.0050/ll.17-29) shows that the step of depositing at least one layer of conductive metal comprises depositing a plurality of metal layers (e.g., a plurality of metal layers is deposited to form the slanted gate field plate 180).
Regarding claim 15, Khalil (see, e.g., pars. 0046/ll.12-13 and 0050/ll.8-16) teaches that depositing and patterning gate metal to form the gate metal field plate 180 comprises a lift-off metal process. Additionally, although Khalil similarly teaches that depositing and patterning gate metal is used to form the gate contact (see, e.g., pars.0045/ll.6-10 and 0046/ll.12-13), Khalil does not explicitly specify that forming the gate contact may be done through a “lift-off” metal process. Khalil, however, does teach that the gate contact may be formed through various methods, including a method akin to a lift-off metal process (see, e.g., par.0047). Furthermore, Khalil teaches lift-off metal processes to be suitable for the formation of contacts (see, e.g., pars.0041/ll.34-37 and 0050/ll.8-16).
Khalil is evidence showing that one of ordinary skill in the art would appreciate that forming a gate contact through a method comprising a lift-off metal process would be equivalent to forming a gate contact through any other method, and that such differences would result in no unexpected change in the performance of the device of Khalil. That is, both contact formation methods of Khalil would yield the predictable result of appropriately and suitably forming a conductive gate structure for a GaN semiconductor power transistor.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use either a lift-off metal process in the step of depositing and patterning gate metal to form the gate contact of Khalil, or to use any other contact-forming process, because these were recognized as equivalents in the semiconductor art for their use as contact-forming methods, and selecting among known equivalents would be within the level of ordinary skill in the art. Furthermore, both methods would yield the predictable result of suitably forming a conductive gate structure for a GaN semiconductor power transistor. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Regarding claim 16, Khalil (see, e.g., pars. 0045/ll.6-10, 0046/ll.12-13, 0047/ll.21-23, and 0050/ll.45-48) shows that depositing and patterning gate metal to form gate contact 150 and the gate metal field plate 180 comprises deposition and etching of the gate material.
Regarding claim 18, Khalil (see, e.g., fig. 1) shows the passivation layer 130 being a first passivation layer. Additionally, Glass (see, e.g., Glass: fig. 2 and par.0057/ll.19-20) shows that the device comprises an enhancement-mode GaN semiconductor power transistor 200.
Furthermore, Khalil (see, e.g., figs. 1 and 9A and par.0048/ll.1-7) shows that the second patterning process of Khalil’s dielectric layer 170 forms a slanted opening (unlabeled opening/dip in 170 laterally between the horizontal centers of 150 and 160) having multiple slanted sidewalls. However, Khalil fails to specify that Khalil’s second patterning process of the dielectric layer is a second etch process comprising a wet etch. Kuo, in the same field of endeavor, teaches wet etching to be suitable for removing material to create a slanted opening shape in a dielectric layer, and additionally asserts that wet etching allows the removal of material from the dielectric layer to not substantially affect the materials of nearby dielectric and doped structures (see, e.g., Kuo: par.0033/ll.26-33). See the comments stated above in paragraphs 34-36 with respect to claim 11, which are considered to be inherited and repeated here.
Additionally, Khalil fails to specify that Khalil’s epitaxial layer structure further comprises a p-doped GaN layer. Lei, in the same field of endeavor, teaches that enhancement-mode transistors comprising a p-doped GaN layer achieve a good balance between achieving normally-off operation and ease of mass production (see, e.g., Lei: par.0002/ll.4-11). Furthermore, Lei shows such a transistor having an epitaxial layer structure 102/104/106/252, wherein Lei further teaches the inclusion of a p-doped GaN layer is integral to ensuring the transistor is operable as an enhancement-mode transistor (see, e.g., Lei: fig. 1A and par.0053).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Khalil’s GaN semiconductor power transistor be constructed as an enhancement-mode GaN semiconductor power transistor and to have Khalil’s epitaxial layer structure further include a p-doped GaN layer, as taught by Lei, so as to expand the applications of Khalil’s transistor while achieving a good balance between achieving normally-off operation and ease of mass production while also ensuring that such a transistor is operable. With regards to the other language recited in claim 18, see the comments stated above in paragraph 26.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Khalil/Lei/Kuo/Glass in view of Coffie (COFFIE ROBERT: “Slant Field Plate Model for Field-Effect Transistors", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE, USA, vol. 61, no. 8, 1 August 2014 (2014-08-01), pages 2867-2872).
Regarding claim 12, Khalil/Lei/Kuo/Glass shows most aspects of the invention (see paragraphs 30-38 above). Furthermore, Khalil (see, e.g., pars.0032/ll.17-19) teaches that the slanted gate field plate 180 reduces and shapes the electrical field under the slanted gate field plate between the gate contact 150 and the drain contact 145. However, Khalil fails to specify that a slant angle of the slanted gate field plate is configured to shape this electric field. Coffie, in the same field of endeavor, teaches that adjusting the slant angle of slanted gate field plates to an optimal angle yields significant improvements in electric field management (see, e.g., Coffie: introduction/ll.16-18 and conclusion).
Therefore, it would have been obvious to one of ordinary skill in the art to have a slant angle of Khalil’s slanted field fate configured to shape an electric field, as taught by Coffie, so as to significantly improve the management of the electric field present under Khalil’s slanted gate field plate and between Khalil’s gate contact and drain contact. With regards to the other language recited in claim 12, see the comments stated above in paragraphs 23-24.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Khalil/Lei/Kuo/Glass in view of Grote (US 2024/0222442).
Regarding claim 17, Khalil (see, e.g., fig. 1) shows the passivation layer 130 being a first passivation layer. Additionally, Glass (see, e.g., Glass: fig. 2 and par.0057/ll.19-20) shows the GaN semiconductor transistor 200 being an enhancement-mode GaN semiconductor power transistor.
However, Khalil fails to specify that Khalil’s epitaxial layer structure further comprises a p-doped GaN layer. Lei, in the same field of endeavor, teaches that enhancement-mode transistors comprising a p-doped GaN layer achieve a good balance between achieving normally-off operation and ease of mass production (see, e.g., Lei: par.0002/ll.4-11). Furthermore, Lei shows such a transistor having an epitaxial layer structure 102/104/106/252, wherein Lei further teaches the inclusion of a p-doped GaN layer is integral to ensuring the transistor is operable as an enhancement-mode transistor (see, e.g., Lei: fig. 1A and par.0053).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Khalil’s GaN semiconductor power transistor be constructed as an enhancement-mode GaN semiconductor power transistor and to have Khalil’s epitaxial layer structure further include a p-doped GaN layer, as taught by Lei, so as to expand the applications of Khalil’s transistor while achieving a good balance between achieving normally-off operation and ease of mass production while also ensuring that such a transistor is operable.
Additionally, although Khalil shows that the etching of Khalil’s gate contact opening comprising etching through the first passivation layer (see, e.g., par.0046/ll.1-4), Khalil fails to specify that Khalil’s method includes providing a second passivation layer and that the etching of the gate contact opening comprising etching the gate contact opening through the first and second passivation layers. Grote, in the same field of endeavor, teaches a method for fabricating a GaN semiconductor power transistor 100, wherein a passivation layer 130 comprising a second passivation layer 133 is provided on passivation layer 130’s first passivation layer 131, and gate contact openings 360 (i.e., a gate contact opening formed through 131 and a gate contact opening formed through 132) are etched through the first and second passivation layers (see, e.g., Grote: figs. 3A-3F and 0064/ll.1-5).
Grote is evidence showing that one of ordinary skill in the art would appreciate that having gate contact openings etched through a first and second passivation layer would be equivalent to having gate contact openings etched through only a first passivation layer, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Khalil. That is, the passivation layer structures of both Khalil and Grote would yield the predictable result of providing an insulating surrounding and supporting structure for the formation of a gate contact.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either gate contact openings etched through a first and second passivation layer, as taught by Grote, or gate contact openings etched through a first and second passivation layer would be equivalent to having gate contact openings etched through only a first passivation layer, as taught by Khalil, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an insulating surrounding and supporting structure for the formation of a gate contact. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
However, Khalil fails to specify the creation of multiple gate contact openings. Lei, in the same field of endeavor, teaches a method for fabricating a GaN semiconductor power transistor 100, wherein a passivation/dielectric layer 220 (see, e.g., Lei: figs. 2A-4F and pars.0037/ll.13-15 and 0039/ll.7-9) is etched to create multiple gate contact openings 230, 232 such that a continuous gate contact 114 is formed filling the multiple contact openings (see, e.g., Lei: figs. 2A-4F and par.0040). See the comments stated above in paragraphs 31-33 regarding the gate contact openings, which are considered to be inherited and repeated here. With regards to the other language recited in claim 17, see the comments stated above in paragraph 25.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814