DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendment to the title is noted, however, it is still deemed to be not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “DISPLAY DEVICE WITH CONTACT PATTERN AND LINE HAVING PLURALITY OF OPENINGS”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8, 11-14 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Na et al. (US 2020/0372375 A1; hereinafter, “Na”, prior art of record) in view of Byun et al. (US 2019/0006442 A1; hereinafter, “Byun-II”).
Regarding claims 1-8:
re claim 1, Na discloses (in Figs. 1 and 12) a display device comprising:
a substrate 100 [0065] defining a display area DA [0049] and a non-display area PA [0049] adjacent to the display area;
a first line BP1 [0059] disposed in the non-display area on the substrate;
a first via insulating layer 160 [0069] disposed on the first line and defining a first opening (e.g., opening for contact with VDD2 in Fig. 12) positioned on at least a portion of the first line;
a second line VDD2/VDD1 [0059] disposed on the first via insulating layer 160 and defining an opening pattern (e.g., opening between VDD2 and VDD1) positioned on the first via insulating layer 160 ; and
a second via insulating layer 170/180/190/310 [0070-0071] disposed on the second line VDD2/VDD1 and including a contact pattern (e.g., a valley pattern defined by layer 170/180/190/310) positioned on at least a portion of the opening pattern (e.g., opening between VDD2 and VDD1) of the second line;
re claim 2, the display device of claim 1, wherein the opening (e.g., opening for contact with VDD2 in Fig. 12) defined in the first via insulating layer in the non-display area is positioned on the first line BP1;
re claim 3, the display device of claim 1, wherein the second via insulating layer 170/180/190/310 fills the first opening pattern (e.g., opening between VDD2 and VDD1);
re claim 4, the display device of claim 3, wherein the second via insulating layer contacts 170/180/190/310 the first via insulating layer 160 in the opening pattern;
re claim 5, the display device of claim 1, wherein the second line VDD2/VDD1 is positioned on at least a portion of the first line BP1;
re claim 6, the display device of claim 1, wherein the second line VDD2/VDD1 contacts the first line BP1 through the opening defined in the first via insulating layer;
re claim 7, the display device of claim 1, further comprising:
a fan-out line FL [0052] disposed in the non-display area on the substrate and positioned on [a lower side of] the first line BP1; and
re claim 8, the display device of claim 7, wherein the fan-out line FL includes: a first fan-out line FL1; and a second fan-out line FL2 disposed on [a side of] the first fan-out line FL1 (Fig. 12) and spaced apart from the first fan-out line in plan view (e.g., Fig. 12 is viewed from the top).
Na does not disclose the second line VDD2/VDD1 comprising a plurality of second openings. However, Byun-II teaches, in a similar device, power supply wiring 71/72 (Fig. 2 and [0032, 0037]) comprising a plurality of holes 72h (Fig. 2 and [0042]) that provide a path for discharging gas in an underlying insulating layer due to heat during manufacturing.
It would have been obvious to one of ordinary skill in the art to modify Na by incorporating a plurality of second openings in the second line, as taught by Byun-II, because the modification would provide a path for discharging gas in an underlying insulating layer due to heat during manufacturing.
Regarding claims 11-14 and 16-20:
re claim 11, Na discloses (in Figs. 1 and 12) a display device comprising:
a substrate 100 defining a display area DA and a non-display area PA adjacent to the display area;
a plurality of fan-out lines FL (Fig. 1) disposed in the non-display area PA on the substrate;
a first power supply line BP1 [0020 and 0059] disposed on the plurality of fan-out lines FL and positioned on at least a portion of the plurality of fan-out lines (Fig. 12);
a first via insulating layer 160 disposed on the first power supply line BP1 and defining a first opening (e.g., opening for contact with VDD2 in Fig. 12) that is positioned on at least a portion of the first power supply line BP1;
a second power supply line VDD2/VDD1 disposed on the first via insulating layer 160 and defining an opening pattern (e.g., opening between VDD2 and VDD1) positioned on the first via insulating layer ; and
a second via insulating layer 170/180/190/310 disposed on the second power supply line VDD2/VDD1 and including a contact pattern (e.g., a valley pattern defined by layer 170/180/190/310) positioned on at least a portion of the opening pattern of the second power supply line;
re claim 12, the display device of claim 11, wherein the plurality of fan-out lines FL includes a first fan-out line (e.g., one of the fan-out lines in Fig. 1), a second fan-out line FL1 (Fig. 12) disposed on the first fan-out line, and a third fan-out line FL2 (Fig. 12) disposed on the second fan-out line;
re claim 13, the display device of claim 12, wherein the first, second and third fan-out lines are spaced apart from each other in plan view (Fig. 1);
re claim 14, the display device of claim 13, further comprising: an insulating layer 140 (Fig. 12) disposed between the third fan-out line F2 and the first power supply line BP1;
re claim 16, the display device of claim 11, wherein the opening (e.g., opening for contact with VDD2 in Fig. 12) defined in the first via insulating layer 160 in the non-display area is positioned on the first power supply line BP1;
re claim 17, the display device of claim 11, wherein the second via insulating layer 170/180/190/310 fills the opening pattern (e.g., opening between VDD2 and VDD1);
re claim 18, the display device of claim 17, wherein the second via insulating layer 170/180/190/310 contacts the first via insulating layer 160 through the opening pattern;
re claim 19, the display device of claim 11, wherein the second power supply line VDD2/VDD1 is positioned on at least a portion of the first power supply line BP1; and
re claim 20, the display device of claim 11, wherein the second power supply line VDD2/VDD1 contacts the first power supply line BP1 through the first opening defined in the first via insulating layer 160.
Na does not disclose the second line VDD2/VDD1 comprising a plurality of second openings. However, Byun-II teaches, in a similar device, power supply wiring 71/72 (Fig. 2 and [0032, 0037]) comprising a plurality of holes 72h (Fig. 2 and [0042]) that provide a path for discharging gas in an underlying insulating layer due to heat during manufacturing.
It would have been obvious to one of ordinary skill in the art to modify Na by incorporating a plurality of second openings in the second line, as taught by Byun-II, because the modification would provide a path for discharging gas in an underlying insulating layer due to heat during manufacturing.
Claim(s) 1, 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. (US 2020/0273940 A1; hereinafter, “Byun”) in view of Byun-II.
Regarding claims 1, 9 and 10:
re claim 1, Byun discloses (in Fig. 17) a display device comprising:
a substrate 105 [0143] defining a display area 10 [0055] and a non-display area 22 [0056] adjacent to the display area;
a first line 351 [0065] disposed in the non-display area on the substrate;
a first via insulating layer 400 [0090] disposed on the first line and defining a first opening 401 [0109] positioned on at least a portion of the first line;
a second line 352 [0065] disposed on the first via insulating layer 400 and defining an opening pattern (e.g., opening between 401 and 402 in Fig. 17) positioned on the first via insulating layer 400 ; and
a second via insulating layer 275/371 (Figs. 12, 17 and [0090]) disposed on the second line 352 and including a contact pattern (e.g., valley pattern defined by 275/371) positioned on at least a portion of the opening pattern (e.g., opening between 401 and 402 in Fig. 17) of the second line 352;
re claim 9, the display device of claim 1, further comprising: a common electrode 340 [0064] disposed on the second via insulating layer 275/371; and
re claim 10, the display device of claim 9, wherein the common electrode 340 contacts the second line 352 through the contact pattern (e.g., valley pattern defined by 275/371) defined in the second via insulating layer 275/371.
Byun does not disclose the second line 352 comprising a plurality of second openings. However, Byun-II teaches, in a similar device, power supply wiring 71/72 (Fig. 2 and [0032, 0037]) comprising a plurality of holes 72h (Fig. 2 and [0042]) that provide a path for discharging gas in an underlying insulating layer due to heat during manufacturing.
It would have been obvious to one of ordinary skill in the art to modify Na by incorporating a plurality of second openings in the second line, as taught by Byun-II, because the modification would provide a path for discharging gas in an underlying insulating layer due to heat during manufacturing.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Na (in view of Byun-II) as applied to claim 14 above, and further in view of Byun.
Regarding claim 15:
Na (in view of Byun-II) renders claim 14 obvious but does not disclose the insulating layer 140 includes an organic insulating material. Na discloses the insulating layer 140 may include silicon oxide [0115]. However, Byun teaches, in a similar display, an organic layer could be incorporated to acquire a flexible layer/substrate (e.g., see Byun [0091]).
It would have been obvious to one of ordinary skill in the art to modify Na by incorporating an organic insulating layer with the insulating layer 140 because Byun shows/teaches such an incorporation could provide a flexible layer/substrate of the display.
Remarks
The objection to the title is maintained because the amendment is not deemed to be descriptive because a display device typically includes a contact pattern.
Applicant’s remarks have been fully considered but are moot in view of the new grounds of rejections necessitated by the amendments to the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892