DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 10/21/2025 without traverse to prosecute the claims of Invention II, claims 14-20 and new claims 21-33 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/14/2023, 8/21/2024, and 3/31/2025 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Claim 21 fragment, “…forming a first conductive feature in the second and third openings and a second conductive feature in the third opening,…” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. FIG. 3D does not show the a single conductive feature in both of the second and third openings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 25 is objected to because of the following informalities:
Claim 25 states, “…depositing a dielectric material ono the etch stop layer, wherein the dielectric…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Liu et al. (CN 112151500 A) and Boyanov et al. (US 20150294935 A1, given in IDS).
Re Claim 14 Ho teaches a method, comprising:
forming a patterned resist layer (P2, page 6 par 4, FIG. 1E) over a dielectric layer (112, FIG 1A, page 5 par 5, “…the base material 112 can be a rigid base material composed of a glass fiber resin substrate…” -- a glass fiber resin substrate is a form of a dielectric material) wherein the patterned resist layer (P2) includes a plurality of openings having different critical dimensions (FIG. 1E);
forming a plurality of conductive features (150a, page 6 pare 5) in the plurality of openings (FIG. 1F,
removing the patterned resist layer (P2, FIG. 2G);
Ho does not teach each conductive feature of the plurality of conductive features partially fills a corresponding opening of the plurality of openings, and the plurality of conductive features have different widths and substantially the same height.
Liu teaches each conductive feature (234, page 7 par 6) of the plurality of conductive features partially fills a corresponding opening (230) of the plurality of openings, and the plurality of conductive features (234) have different widths and substantially the same height (FIG. 2A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Liu into the structure of Ho since Liu teaches a method of forming a semiconductor device.
The ordinary artisan would have been motivated to modify Liu in combination with Ho in the above manner for the motivation of optimally forming the conductive features in the mask openings to allow for the device’s density can be controlled. Page 2 par 3 states, “The size is scaled to become smaller and smaller, so that the density of the functional unit can be improved on the surface of the limited semiconductor chip substrate.”
Ho in view of Liu does not teach depositing an etch stop layer on the dielectric layer and around the plurality of conductive features; and
depositing a dielectric material on the etch stop layer and over the plurality of conductive features.
Boyanov teaches depositing an etch stop layer on the dielectric layer and around the plurality of conductive features (Metal A and C, FIG. 2C); and
depositing a dielectric material on the etch stop layer and over the plurality of conductive features (Metal A and C, FIG. 2F).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Boyanov into the structure of Ho in view of Liu since Boyanov teaches a method of forming a semiconductor device.
The ordinary artisan would have been motivated to modify Boyanov in combination with Ho in view of Liu in the above manner for the motivation of forming at etch stop layer and a dielectric layer over the conductive features to allow the device to function optimally in a circuit. Boyanov [0015] states, “Thus, and in accordance with one embodiment, techniques are provided for forming conductive interconnect features, such as through-vias and damascene features (e.g., trench/via structures) for electrically connecting one layer of an integrated circuit to another layer of that integrated circuit.”
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Liu et al. (CN 112151500 A) and Boyanov et al. (US 20150294935 A1, given in IDS) and further in view of Shaviv et al. (CN 108475625 A).
Re Claim 15 Kim in view of Boyanov teaches the method of claim 14, but does not teach the plurality of conductive features are formed by an electrochemical deposition process.
Shaviv page 7 par 3 states, “…a second metal layer 32 (e.g., a conformal electrochemical deposition metal layer, see FIG. 1D).” FIG. 1 F shows a single 32 element, but the process can be repeated for multiple conductive features.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Shaviv into the structure of Ho in view of Liu and Boyanov since Shaviv teaches a method of integrating a electrochemical deposition to forma semiconductor device.
The ordinary artisan would have been motivated to modify Shaviv in combination with Ho in view of Liu and Boyanov in the above manner for the motivation of depositing the conductive contacts electrochemically to help optimize the device performance. Page 2 par 3 states, “improving IC performance that typically accompanies the device area decreases and/or increases the device density. improve device density will cause for reducing through hole and groove dimension (width) forming interconnection.”
Re Claim 16 Kim in view of Boyanov and Shaviv teaches the method of claim 15, but does not explicitly teach a current density of the electrochemical deposition process ranges from about 0.1 ampere/square decimeter to about 1 ampere/square decimeter.
Shaviv page 9 par 4 teaches, “In some exemplary embodiments of the present disclosure, the deposition current density for an ECD of rare chemicals range can be 1mA/cm2 (amperes per square centimeter) to 6mA/cm2 or range compared with the concentrated chemical can be 1mA/cm2 to 30mA/cm2.” (1 A/dm² = 10 mA/cm².)
The ordinary artisan would have been motivated to modify Shaviv in combination with Ho in view of Liu, Boyanov, and Shaviv in the above manner for the motivation of finding optimal current density.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal current density
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Liu et al. (CN 112151500 A), Boyanov et al. (US 20150294935 A1, given in IDS), and Shaviv et al. (CN 108475625 A), and further in view of Zhu et al. (CN 103882494 A).
Re Claim 17 Kim in view of Boyanov and Shaviv teaches the method of claim 15, but does not teach a molar concentration of CuSO4 used in the electrochemical deposition process ranges from about 0.1 M to about 0.3 M.
Zhu teaches [0017], “…the molar concentration of CuSO4 in the electrolyte is 0.4M…”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhu into the structure of Ho in view of Liu, Boyanov, and Shaviv since Zhu teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Zhu in combination with Ho in view of Liu, Boyanov, and Shaviv in the above manner for the motivation of finding ideal molar concentration of CuSO4.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal CuSO4 molar concentration.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Liu et al. (CN 112151500 A), Boyanov et al. (US 20150294935 A1, given in IDS), Shaviv et al. (CN 108475625 A), and Zhu et al. (CN 103882494 A) and further in view of Luo et al. (CN 110718399 B).
Re Claim 18 Kim in view of Boyanov, Shaviv, and Zhu teaches the method of claim 17, but does not teach a molar concentration of H2SO4 used in the electrochemical deposition process ranges from about 1 M to about 3 M.
Luo teaches page 4 par 4, “…the concentration of the sulphuric acid is 1M,…”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Luo into the structure of Ho in view of Liu, Boyanov, Shaviv, and Zhu since Luo teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Luo in combination with Ho in view of Liu, Boyanov, Shaviv, and Zhu in the above manner for the motivation of finding optimal sulfuric acid concentration levels.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal concentration levels for H2SO4.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Liu et al. (CN 112151500 A), Boyanov et al. (US 20150294935 A1, given in IDS), Shaviv et al. (CN 108475625 A), Zhu et al. (CN 103882494 A), and Luo et al. (CN 110718399 B) and further in view of Pabelico et al. (KR 20170002606 A).
Re Claim 19 Ho in view of Liu, Boyanov, Shaviv, Zhu, and Luo teaches the method of claim 18, but does not teach a molar concentration of a leveler used in the electrochemical deposition process ranges from about 0.025 M to about 0.075 M.
Pabelico teaches page 6 par 5 an ECD process and page 9 par 3 using “…a 1.0 ml / l leveler …” (1.0 ml/l = 1)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Pabelico into the structure of Ho in view of Liu, Boyanov, Shaviv, Zhu, and Luo since Pabelico teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Pabelico in combination with Ho in view of Liu, Boyanov, Shaviv, Zhu, and Luo in the above manner for the motivation of finding optimal leveler concentration used in the electrochemical deposition process.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal level values to optimize the process.
Re Claim 20 Ho in view of Liu, Boyanov, Shaviv, Zhu, Luo, and Pabelico teaches the method of claim 19, but does not explicitly teach a bath temperature of the electrochemical deposition process ranges from about 30 degrees Celsius to about 40 degrees Celsius.
Pabelico teaches page 6 par 4, “Suitable bath temperatures may range from about 18 degrees Celsius to about 60 degrees Celsius.”
The ordinary artisan would have been motivated to modify Pabelico in combination with Ho in view of Liu, Boyanov, Shaviv, Zhu, Luo, and Pabelico in the above manner for the motivation of finding optimal current density.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal electrochemical deposition processing temperatures.
Claims 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (CN 115020318 A) in view of Boyanov et al. (US 20150294935 A1, given in IDS), Ho (TW I758138 B), and Liu et al. (CN 112151500 A).
Re Claim 21 Kim teaches a method, comprising:
depositing a dielectric layer (106, page 7 par 4) over a conductive layer (102a, page 7 par 4);
forming a first opening (122, FIG.3 and 4) in the dielectric layer (106);
depositing a barrier layer (146, page 8 par 1) on the dielectric layer (106) and in the first opening (FIG. 5);
Kim does not teach depositing a seed layer on the barrier layer over the dielectric layer and in the first opening;
Boyanov teaches depositing a seed layer on the barrier layer over the dielectric layer and in the first opening (FIG. 2A, [0018] “In some embodiments, the trench where the metal lines are formed may be lined with a barrier layer (to prevent electromigration into the ILD) and/or a seed layer (to assist in metallization of the trench), and/or any other desired layers.”);
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Boyanov into the structure of Kim since Boyanov teaches a method of forming a semiconductor device.
The ordinary artisan would have been motivated to modify Boyanov in combination with Kim in the above manner for the motivation of using a seed layer to help form the later added conductive layer. Boyanov [0015] states, “Thus, and in accordance with one embodiment, techniques are provided for forming conductive interconnect features, such as through-vias and damascene features (e.g., trench/via structures) for electrically connecting one layer of an integrated circuit to another layer of that integrated circuit.”
Kim in view of Boyanov does not teach forming a patterned resist layer on the seed layer, wherein the patterned resist layer comprises second and third openings, and the first opening is exposed in the second opening; and
forming a first conductive feature in the first and second openings and a second conductive feature in the third opening, wherein the first conductive feature fills the first opening and partially fills the second opening, and the second conductive feature partially fills the third opening.
Ho teaches forming a patterned resist layer (P2, page 6 par 4) on the seed layer (145, page 6 par 5), wherein the patterned resist layer (P2) comprises second and third openings, and the first opening is exposed in the second opening; and
forming a first conductive feature (150a, page 6 par 5) in the first and second openings and a second conductive feature in the third opening, wherein the first conductive feature fills the first opening and fills the second opening, and the second conductive feature fills the third opening (see modified figures below).
See modified FIG. 1E and 1F below
PNG
media_image1.png
674
910
media_image1.png
Greyscale
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ho into the structure of Kim in view of Boyanov since Ho teaches a method of forming a semiconductor device.
The ordinary artisan would have been motivated to modify Ho in combination with Kim in view of Boyanov in the above manner for the motivation of integrating resist layers over the seed layer and then forming conductive layers in the opening of the resist layer and under layers in a manner to optimize the manufacturing process and keep costs to a minimum. Page 2 par 4 states, “The present invention provides a chip package structure and a manufacturing method thereof, which are relatively safe and simple to manufacture, and can effectively reduce manufacturing costs and improve product yield.”
Kim in view of Boyanov and Ho does not teach the first conductive feature partially fills the second opening, and the second conductive feature partially fills the third opening.
Liu teaches the first conductive feature (234, page 7 par 6) partially fills the second opening (230 in middle, FIG. 2B), and the second conductive feature (234) partially fills the third opening (230 on right, FIG. 2A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Liu into the structure of Kim in view of Boyanov and Ho since Liu teaches a method of forming a semiconductor device.
The ordinary artisan would have been motivated to modify Liu in combination with Kim in view of Boyanov and Ho in the above manner for the motivation of optimally forming the conductive features in the mask openings to allow for the device’s density can be controlled. Page 2 par 3 states, “The size is scaled to become smaller and smaller, so that the density of the functional unit can be improved on the surface of the limited semiconductor chip substrate.”
Re Claim 22 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 21, further comprising removing the patterned resist layer (Ho, P2) to expose portions of the seed layer (145, FIG. 1G).
Re Claim 23 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 22, further comprising removing the exposed portions of the seed layer (Ho, 145) and portions of the barrier layer (use 140, page 9 states is has titanium, a known capping layer) located under the exposed portions of the seed layer (145, FIG. 1G).
Re Claim 24 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 23, further comprising depositing an etch stop layer on the dielectric layer and around the first and second conductive features (Boyanov, use Metal A and Metal C, FIG. 2C).
Re Claim 25 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 24, further comprising depositing a dielectric material onto the etch stop layer, wherein the dielectric material is deposited between the first and second conductive features and over the first and second conductive features (Boyanov, use Metal A and Metal C, FIG. 2C).
Re Claim 26 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 21, wherein the second and third openings (see 2nd and 3rd opening is figure under claim 21, 2nd opening is wider and 3rd opening) have different critical dimensions.
Re Claim 27 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 26, wherein the first and second conductive features (see 1st and 2nd conductive feature is figure under claim 21, 1st conductive feature is wider than 2nd conductive feature) have different widths.
Re Claim 28 Kim in view of Boyanov, Ho, and Liu teaches the method of claim 27, wherein the first (Boyanov, Metal A) and second conductive features (Boyanov, Metal C) have a same height (FIG. 2F).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Shaviv et al. (CN 108475625 A) and Zhu et al. (CN 103882494 A).
Re Claim 29 Ho teaches a method, comprising:
forming a patterned resist layer (P2, FIG. 1E, page 6 par 4) over a dielectric layer (112, FIG. 1A, page 5 par 5, “…112 can be a rigid base material composed of a glass fiber resin substrate…”), wherein the patterned resist layer (P2) includes a plurality of openings having different critical dimensions (See width of 2nd opening and 3rd opening in modified FIG. 1E below claim 21);
forming a plurality of conductive features (150a, page 13 par 5) in the plurality of openings (FIG. 1F); and
removing the patterned resist layer (P2, FIG. 1G).
Ho does not teach an electrochemical deposition process, wherein a current density of the electrochemical deposition process ranges from about 0.1 ampere/square decimeter to about 1 ampere/square decimeter.
Shaviv page 9 par 4 teaches, “In some exemplary embodiments of the present disclosure, the deposition current density for an ECD of rare chemicals range can be 1mA/cm2 (amperes per square centimeter) to 6mA/cm2 or range compared with the concentrated chemical can be 1mA/cm2 to 30mA/cm2.” (1 A/dm² = 10 mA/cm².); and
the electrochemical deposition process uses CuSO4 (Page 11 par 7 sates, “…ECD acidic copper chemicals can include, for example, copper sulfate,…”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Shaviv into the structure of Ho since Shaviv teaches a method of forming a semiconductor device.
The ordinary artisan would have been motivated to modify Shaviv in combination with Ho in the above manner for the motivation optimizing the electrochemical deposition process. Page 8 par 8 states, “…high sheet resistance may be completed electrically connected during the electrochemical deposition process causes the workpiece from overheating.”
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal current density
Ho in view of Shaviv does not teach molar concentration used in the electrochemical deposition process ranges from about 0.1 M to about 0.3 M.
Zhu teaches [0017], “…the molar concentration of CuSO4 in the electrolyte is 0.4M…”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhu into the structure of Ho in view of Shaviv since Zhu teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Zhu in combination with Ho in view of Shaviv in the above manner for the motivation of finding ideal molar concentration of CuSO4.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal CuSO4 molar concentration.
Claims 30 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Shaviv et al. (CN 108475625 A) and Zhu et al. (CN 103882494 A) and in further view of Pabelico et al. (KR 20170002606 A).
Re Claim 30 Ho in view of Shaviv and Zhu teaches the method of claim 29, but does not teach a molar concentration of a leveler used in the electrochemical deposition process ranges from about 0.025 M to about 0.075 M.
Pabelico teaches page 6 par 5 an ECD process and page 9 par 3 using “…a 1.0 ml / l leveler …” (1.0 ml/l = 1)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Pabelico into the structure of Ho in view of Shaviv and Zhu since Pabelico teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Pabelico in combination with Ho in view of Shaviv and Zhu in the above manner for the motivation of finding optimal leveler concentration used in the electrochemical deposition process.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal level values to optimize the process.
Re Claim 32 Ho in view of Shaviv, Zhu, and Pabelico teaches the method of claim 29, but does not explicitly teach a processing temperature of the electrochemical depositing process ranges from about 30 degrees Celsius to about 40 degrees Celsius.
Pabelico teaches page 6 par 4, “Suitable bath temperatures may range from about 18 degrees Celsius to about 60 degrees Celsius.”
The ordinary artisan would have been motivated to modify Pabelico in combination with Ho in view of Shaviv, Zhu, and Pabelico in the above manner for the motivation of finding bath processing temperatures.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal electrochemical deposition processing temperatures.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Shaviv et al. (CN 108475625 A), Zhu et al. (CN 103882494 A), and Pabelico (KR 20170002606 A) in further view of Han et al. (WO 2023014524 A1).
Re Claim 31 Ho in view of Shaviv, Zhu, and Pabelico teaches the method of claim 30, but does not teach the leveler comprises derivatives of pyridinium or imidazolium.
Han teaches the leveler comprises a pyridinium derivative ([0076] “The leveler may also comprise a substituted pyridyl compound, which may be, for example, a pyridinium compound and, in particular, a quaternized pyridinium salt.”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ho into the structure of Ho in view of Shaviv, Zhu, and Pabelico since Han teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Han in combination with Ho in view of Shaviv, Zhu, and Pabelico in the above manner for the motivation of using a pyridinium derivative for the leveler to help maintain the device’s copper microstructure. [0040] states, “Based thereon, the inventors of the present invention have found that certain types of accelerators and levelers can function synergistically with nanotwin producing suppressors without compromising the nanotwinned copper microstructure.”
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (TW I758138 B) in view of Shaviv et al. (CN 108475625 A) and Zhu et al. (CN 103882494 A) and further in view of Luo et al. (CN 110718399 B).
Re Claim 33 Ho in view of Shaviv and Zhu teaches the method of claim 29, but does not teach a molar concentration of H2SO4 used in the electrochemical deposition process ranges from about 1 M to about 3 M.
Luo teaches page 4 par 4, “…the concentration of the sulphuric acid is 1M,…”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Luo into the structure of Ho in view of Shaviv and Zhu since Luo teaches integrating an electrochemical deposition process into a semiconductor building process.
The ordinary artisan would have been motivated to modify Luo in combination with Ho in view of Shaviv and Zhu in the above manner for the motivation of finding optimal sulfuric acid concentration levels.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal concentration levels for H2SO4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/21/26