Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/19/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 9-28 without traverse in the reply filed on 11/03/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-14, 16-19, and 21-22, 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al US 20210225916 A1, in view of Ahn et al US 20140263962 A1. Hsieh et al and Ahn et al will be referenced to as Hsieh and Ahn respectively henceforth.
Regarding Claim 9,
Hsieh teaches:
“A method, comprising:
forming one or more trenches (form plural trenches 110T, [0065], FIG. 21) in a pixel array region (pixel array region 102, [0050], FIG. 12) of a substrate (substrate 110, [0071], FIG. 24);
depositing a first dielectric layer over the substrate and in the one or more trenches (dielectric layer 160, [0066], FIG.21: 160 is deposited into 110T.);
forming one or more openings in the first dielectric layer (one or more trenches 160T1 and 160T2, [0067], FIG. 22);
depositing a light blocking layer over the first dielectric layer and in the one or more openings (light blocking layer 170, [0068], FIG. 23);
patterning the light blocking layer to form a light blocking structure in a black level correction region (BLC region 104, [0069], FIG. 24: 170 is patterned into 174 in 104.), wherein the light blocking structure is in contact with the substrate (FIG. 24: 174 is in contact with 110.);
forming a first opening in the first dielectric layer and the substrate (opening O1, [0054], FIG. 26) in a contact pad region (scribe line region 106, [0030], FIG. 28);”
Hsieh doesn’t substantially teach the entirety of:
“depositing a conductive layer over the substrate and in the first opening;
and patterning the conductive layer to form a contact pad structure, wherein the contact pad structure extends from the contact pad region to the black level correction region.”
However, Ahn teaches:
“depositing a conductive layer over the substrate and in the first opening (Hsieh/Ahn: Hsieh: bonding pad 210, [0074], FIG. 27; Ahn: preliminary first conductive layer 152P, [0119], FIG. 8I);
and patterning the conductive layer to form a contact pad structure (Ahn: conductive layer 152, light-shielding pattern 160, [0124-0125], FIG. 8K: 152P may have a partial removal. The remaining portions of 152P are conductive layer 152 and light-shielding pattern 160. 160 and 152 are connected.), wherein the contact pad structure extends from the contact pad region to the black level correction region (Ahn: optical black sensor area OBS, [0139], FIG. 8K: the contact pad structure comprises 160 and 152. The contact pad structure extends from the contact pad region, pad area PA, to OBS.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Hsieh is modifiable in view of Ahn.
This is because extending the contact pad region to the black level correction region provides the benefit of improving a light-shielding effect in the black level correction region (US 20120086094 A1: [0091]). One of ordinary skill in the art would recognize this benefit as advantageous as the purpose of a black level correction layer is to calibrate a black level in an image sensor. Therefore, improved light-shielding helps to improve that calibration by preventing light from reaching a reference sensor.
Regarding Claim 10,
Hsieh/Ahn teaches:
“The method of claim 9, further comprising forming an interconnect structure on the substrate (Hsieh: interconnect structure 150, [0017], FIG. 18) and flipping over the substrate prior to forming the one or more trenches in the pixel array region of the substrate (Hsieh: [0064], FIGs.18-20: The trenches are formed in FIG. 20. The substrate is flipped in FIG. 19.).”
Regarding Claim 11,
Hsieh/Ahn teaches:
“The method of claim 10, wherein the patterning the light blocking layer removes portions of the first dielectric layer (Hsieh: [0069], FIG. 24: the openings are in 160 and 170.).”
Regarding Claim 12,
Hsieh/Ahn teaches:
“The method of claim 9, further comprising depositing a second dielectric layer over the first dielectric layer after patterning the light blocking layer (Hsieh: dielectric layer 180, [0072], FIG. 25: 180 is formed over the patterned light blocking layer.).”
Regarding Claim 13,
Hsieh/Ahn teaches:
“The method of claim 12, wherein the first opening is formed in the second dielectric layer (Hsieh: [0073], FIG. 26: portions of 180, 160 and 110 are removed to form O1.). ”
Regarding Claim 14,
Hsieh/Ahn teaches:
“The method of claim 13, further comprising forming a buffer oxide layer over the substrate and in the first opening prior to depositing the conductive layer (Hsieh: buffer oxide layer 190, [0073], FIG. 26: The conductive layer is deposited in FIG. 27. 190 is deposited in FIG. 26.).”
Regarding Claim 16,
Hsieh/Ahn teaches:
“A method, comprising:
depositing a first dielectric layer (Hsieh: dielectric layer 160, [0066], FIG. 21) over a substrate (Hsieh: substrate 110, [0071], FIG. 24), wherein the first dielectric layer is deposited in a pixel array region (Hsieh: pixel array region 102, [0050], FIG. 17), a black level correction region (Hsieh: BLC region 104, [0069], FIG. 24), a contact pad region (Hsieh: scribe line region 106, [0030], FIG. 28), and an alignment mark region (Hsieh: alignment mark region 108, [0030], FIG. 29);
forming openings in the first dielectric layer in the black level correction region and the alignment mark region (Hsieh: one or more trenches 160T1 and 160T2, [0067], FIG. 22: 160T1 is 104. 160T2 is in 108);
depositing a light blocking layer over the first dielectric layer and in the openings (Hsieh: light blocking layer 170, [0068], FIG. 23);
removing portions of the light blocking layer in the pixel array region (Hsieh: [0069], FIG. 24: In 102, 170 is patterned to be 172.) and the contact pad region (Hsieh: [0069], FIG. 24: In 106, 170 is patterned to be 170O2.) to form a light blocking grid in the pixel array region (Hsieh: light blocking grid 172) and light blocking structures in the black level correction region (Hsieh: light blocking element 174, [0069], FIG. 24) and the alignment mark region (Hsieh: light blocking element 178, [0069], FIG. 24);
depositing a conductive layer in the pixel array region, the black level correction region, the contact pad region, and the alignment mark region (Hsieh/Ahn: Ahn: preliminary first conductive layer 152P, [0119], FIG. 8I: 152P is deposited over the whole substrate and is then patterned away in regions other than pad area PA and optical black sensor area OBS. Therefore, the conductive layer would be deposited on the alignment mark region in the combination of Hsieh/Ahn and then later removed.), wherein the conductive layer is in contact with the light blocking structure in the black level correction region (Hsieh/Ahn: Ahn teaches a conductive layer 160 which covers OBS. Therefore, the combination of Hsieh/Ahn teaches a conductive layer covering a light blocking structure in the black level correction region.);
and removing portions of the conductive layer in the pixel array region (Ahn: [0132], FIG. 8N: 152P is removed from the active pixel area APS.) and the alignment mark region (Hsieh/Ahn: Ahn: preliminary first conductive layer 152P, [0119], FIG. 8I: 152P is deposited over the whole substrate and is then patterned away in regions other than pad area PA and optical black sensor area OBS. Therefore, the combination of Hsieh/Ahn conductive layer would be deposited on the alignment mark region and then later removed.) to form a contact pad structure extending from the contact pad region to the black level correction region (Ahn: FIG. 8O).”
Regarding Claim 17,
Hsieh/Ahn teaches:
“The method of claim 16, further comprising depositing a second dielectric layer on and in contact with the light blocking grid (Hsieh: dielectric layer 180, [0072], FIG. 25: 180 is formed over the patterned light blocking element 172 in 102.), the light blocking structures, and the first dielectric layer prior to depositing the conductive layer (Hsieh: dielectric layer 180, [0072], FIG. 25: 180 is formed over the patterned light blocking element 174 in 104. 180 is formed in direct contact with 160 in 102.).”
Regarding Claim 18,
Hsieh/Ahn teaches:
“The method of claim 17, further comprising removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the substrate in the contact pad region to expose an isolation layer (Hsieh: isolation layer 134, [0073- 0074], FIGs. 26-27: Portions of dielectric layers 180 and 160 and substrate 110 are removed. Further, 134 is patterned prior to the deposition of bonding pad 210. As such, 134 must be exposed.).”
Regarding Claim 19,
Hsieh/Ahn teaches:
“The method of claim 18, further comprising depositing a buffer oxide layer in the pixel array region, the black level correction region, the contact pad region, and the alignment mark region (Hsieh: buffer oxide layer 190, [0073], FIG. 29: 190 is deposited in 102, 104, 106, and 108.), wherein the buffer oxide layer is in contact with the isolation layer (FIG. 29: 190 is directly on 134.).”
Regarding Claim 21,
Hsieh/Ahn teaches:
“A method, comprising:
depositing a first dielectric layer (Hsieh: dielectric layer 160, [0066], FIG. 21) over a substrate (Hsieh: substrate 110, [0071], FIG. 24), wherein the first dielectric layer is deposited in a pixel array region (Hsieh: pixel array region 102, [0050], FIG. 17), a black level correction region (Hsieh: BLC region 104, [0069], FIG. 24), and a contact pad region (Hsieh: scribe line region 106, [0030], FIG. 28);
removing a portion of the first dielectric layer in the contact pad region to form a first opening (Hsieh: opening O1, [0073], FIG. 26: a portion of 160 is removed in 106.), wherein an isolation layer is exposed in the first opening (Hsieh: isolation layer 134, [0074], FIGs. 26-27: 134 is patterned to expose the conductive lines 154M. During this process, the isolation layer must be exposed prior to the deposition of bonding pad 210.);
removing a portion of the isolation layer to form a second opening (Hsieh: [0074], FIGs. 26-27, annotated FIG. 27 #1: 134 is patterned to expose the conductive lines 154M.), wherein a conductive line is exposed in the second opening (Hsieh: conductive lines 154M, [0074] FIG. 27: A single conductive line 154M is shown in FIG. 27.);
forming a third opening over a portion of the first dielectric layer in the black level correction region (Ahn: [0111], annotated FIG. 8O #1: the third opening is formed over silicon oxide layer 132B.); and
depositing a conductive layer in the first and second openings (Hsieh/Ahn: Ahn: 152P is deposited in pad area PA and optical black sensor area OBS. One of ordinary skill in the art would combine Hsieh and Ahn, by depositing the conductive layer in both the second and third openings for the advantage of improving a light-shielding effect in the OBS region.), wherein the conductive layer is a continuous layer extending from the contact pad region to the black level correction region (Ahn: conductive layer 152, light-shielding pattern 160, [0124-0125], FIG. 8K: 152P may have a partial removal. The remaining portions of 152P are conductive layer 152 and light-shielding pattern 160. 160 and 152 are connected.).”
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Regarding Claim 22,
Hsieh/Ahn teaches:
“The method of claim 21, wherein the conductive layer is electrically coupled to the conductive line (Ahn: [0106], FIG. 8J: 152P is in direct electrical contact with wiring lines 126.).”
Regarding Claim 24,
Hsieh/Ahn teaches:
“The method of claim 21, further comprising forming a light blocking structure (Hsieh: light blocking element 174, [0069], FIG. 24) over the portion of the first dielectric layer in the black level correction region (Hsieh: FIG. 24: 174 is formed from light blocking layer 170 in FIG. 23. This is done by patterning 170.).”
Regarding Claim 25,
Hsieh/Ahn teaches:
“The method of claim 24, further comprising depositing a second dielectric layer on the light blocking structure in the black level correction region and on the portion of the first dielectric layer in the contact pad region (Hsieh: dielectric layer 180, [0072], FIG. 25: 180 is formed over the patterned light blocking element 174 in 104. 180 is formed in direct contact with 160 in 106.). ”
Regarding Claim 26,
Hsieh/Ahn teaches:
“The method of claim 25, wherein the first opening is formed in the second dielectric layer in the contact pad region (Hsieh: [0073], FIG. 26: portions of 180, 160 and 110 are removed to form O1.).”
Regarding Claim 27,
Hsieh/Ahn teaches:
“The method of claim 26, further comprising depositing a buffer oxide layer (Hsieh: buffer oxide layer 190, [0073], FIG. 26) on the second dielectric layer in the black level correction region (Hsieh: FIG. 26) and in the first opening in the contact pad region (Hsieh: FIG. 26). ”
Allowable Subject Matter
Claims 15, 20, 23 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 15,
Hsieh/Ahn fails to explicitly teach:
“forming a second opening in the buffer oxide layer and the second dielectric layer to expose the light blocking structure in the black level correction region;”
In view of the rest of the limitations of claim 14.
Hsieh/Ahn fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. The Examiner did find art in which buffer layers were formed om a second opening in a black level correction region (For example, Ahn). However, the Examiner did not find art in which portions of a buffer oxide layer were removed to form a second opening in view of the limitations of claim 14.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Hsieh/Ahn to reach all of the limitations of the claim.
Regarding Claims 20 and 28, these claims depend on claims 16 and 21 respectively and are allowable for the same reasons as claim 15. That is, the removal of a buffer oxide layer to create an opening exposing a light blocking layer.
Regarding Claim 23,
Hsieh/Ahn fails to explicitly teach :
“wherein the second and third openings are formed simultaneously” In view of the rest of the limitations of claim 21.
Hsieh/Ahn fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record. The Examiner did find art such as US 20230057857 A1, which teaches the simultaneous formation of openings in an optical black region and a pad region. However, Applicant’s second opening is formed within a first opening, which is not taught by US 20230057857 A1.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Hsieh/Ahn to reach all of the limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812