Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Objection
The assignee appears to be misspelled on the ADS: Woflspeed instead of Wolfspeed. Please Correct.
Analysis of Independent Claims Provide First (Dependent Claim Analysis will follow below)
Independent Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,11, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuchiya (Tsuchiya, US 2013/0062622)
In regards to independent claim 1, Tshuchiya teaches a method of forming a semiconductor device, comprising:
providing a first layer, the first layer comprising silicon carbide and having a first conductivity type (Tsuchiya, Item 10 N type conductivity, [0077], “In addition, in the n.sup.--type SiC layer 10b, the n.sup.+-type SiC region (n-type impurity region) 14 of the 4H--SiC structure is formed by, for example, thermal treatment (annealing) with P ion implantation and activation”);
forming a plurality of doped regions in the silicon carbide layer, the plurality of doped regions having a second conductivity type opposite the first conductivity type (Tsuchiya, Item 16 P type conductivity, [0080], “Subsequently, in the n -type SiC layer 10b, the p.sup.+-type SiC region (second p-type impurity region) 16 of the 4H--SiC structure is formed”);
providing a second layer on the first layer, wherein the second layer comprises nickel, and wherein the second layer contacts the plurality of doped regions and contacts the first layer (Tsuchiya, Item 36 Fig. 6 [0098], “a metallic film 36 is formed…More specifically, for example, a nickel film is deposited using sputtering method and the like”), ;
annealing the first layer and the second layer at a first anneal temperature to form a layer of nickel silicide on the first layer (Tsuchiya, [0104], “two-step annealing method is also effective as a method for forming the nickel silicide layer 18. In this case, silicide is formed at a relatively low temperature of about 700 degrees or less as the first step annealing process”);
annealing the first layer and the layer of nickel silicide at a second anneal temperature that is greater than first anneal temperature, to cause the layer of nickel silicide to form ohmic junctions to the plurality of doped regions and to form a Schottky barrier junction to the first layer (Tsuchiya, [0104, “then the second step annealing process is performed at a temperature higher than that of the first step annealing process after the unreacted Ni removing process with acid solution. When this is done, the contact resistance can be further reduced,” [0028], “ Accordingly, a Schottky barrier between the metallic silicide and the n-type impurity region is reduced, and the contact resistance is reduced”).
In regards to independent claim 11, Tshuchiya teaches a method of forming a metal contact on a first layer, the first layer comprising silicon carbide having a first conductivity type (Tsuchiya, Item 10 N type conductivity, [0077], “In addition, in the n.sup.--type SiC layer 10b, the n.sup.+-type SiC region (n-type impurity region) 14 of the 4H--SiC structure is formed by, for example, thermal treatment (annealing) with P ion implantation and activation”), the method comprising:
forming a doped region in the first layer, the doped region having a second conductivity type opposite the first conductivity type (Tsuchiya, Item 16 P type conductivity, [0080], “Subsequently, in the n -type SiC layer 10b, the p.sup.+-type SiC region (second p-type impurity region) 16 of the 4H--SiC structure is formed”);
forming a layer of nickel silicide on the first layer, wherein the layer of nickel silicide contacts the first layer and contacts the doped region (Tsuchiya, Item 36 Fig. 6 [0098], “a metallic film 36 is formed…More specifically, for example, a nickel film is deposited using sputtering method and the like”, [0104], “two-step annealing method is also effective as a method for forming the nickel silicide layer 18. In this case, silicide is formed at a relatively low temperature of about 700 degrees or less as the first step annealing process”); and
annealing the layer of nickel silicide and the first layer at a sufficient temperature to cause the layer of nickel silicide to form an ohmic contact to the doped region and a Schottky barrier junction to the first layer (Tsuchiya, [0104, “then the second step annealing process is performed at a temperature higher than that of the first step annealing process after the unreacted Ni removing process with acid solution. When this is done, the contact resistance can be further reduced,” [0028], “ Accordingly, a Schottky barrier between the metallic silicide and the n-type impurity region is reduced, and the contact resistance is reduced”).
In regards to independent claim 19, Tshuchiya teaches a semiconductor device structure, comprising:
a first layer, wherein the first layer comprises silicon carbide and has a first conductivity type(Tsuchiya, Item 10 N type conductivity, [0077], “In addition, in the n.sup.--type SiC layer 10b, the n.sup.+-type SiC region (n-type impurity region) 14 of the 4H--SiC structure is formed by, for example, thermal treatment (annealing) with P ion implantation and activation”);
a plurality of doped regions in the first layer, the plurality of doped regions having a second conductivity type opposite the first conductivity type (Tsuchiya, Item 16 P type conductivity, [0080], “Subsequently, in the n -type SiC layer 10b, the p.sup.+-type SiC region (second p-type impurity region) 16 of the 4H--SiC structure is formed”); and
a layer of nickel silicide on the first layer, wherein the layer of nickel silicide forms ohmic junctions to the plurality of doped regions and forms a Schottky barrier junction to the silicon carbide layer (Tsuchiya, [0098], “a metallic film 36 is formed…More specifically, for example, a nickel film is deposited using sputtering method and the like”, [0104], “two-step annealing method is also effective as a method for forming the nickel silicide layer 18. In this case, silicide is formed at a relatively low temperature of about 700 degrees or less as the first step annealing process then the second step annealing process is performed at a temperature higher than that of the first step annealing process after the unreacted Ni removing process with acid solution. When this is done, the contact resistance can be further reduced,” [0028], “ Accordingly, a Schottky barrier between the metallic silicide and the n-type impurity region is reduced, and the contact resistance is reduced”).
Dependent Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-10, 12-18, 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuchiya
In regards to dependent claim 2, Tsuchiya teaches wherein the first anneal temperature is less than about 700 C (Tsuchiya, [0104]).
In regards to dependent claim 3, Tsuchiya teaches wherein the second anneal temperature is greater than about 800 C (Tsuchiya, [0104]).
In regards to dependent claim 4, Tsuchiya teaches wherein the second anneal temperature is between about 825 C and 925 C (Tsuchiya, [0104]).
In regards to dependent claim 5, Tsuchiya teaches wherein the first conductivity type is n-type and wherein the second conductivity type is p-type (Tsuchiya, Fig. 1, 14 vs 16).
In regards to dependent claim 6, Tsuchiya teaches wherein the plurality of doped regions comprise implanted regions in the first layer (Tsuchiya, Fig. 1, 14 vs 16).
In regards to dependent claim 7, Tsuchiya teaches wherein the first layer has a doping concentration of less than about 2E16 cm-3 (Tsuchiya, [0032])..
In regards to dependent claim 8, Tsuchiya teaches wherein the plurality of doped regions have a doping concentration greater than about 2E19 cm-3 (Tsuchiya, [0035]).
In regards to dependent claim 9, Tsuchiya teaches wherein the plurality of doped regions comprise junction barrier Schottky regions in the first layer (Tsuchiya, [0028], “ Accordingly, a Schottky barrier between the metallic silicide and the n-type impurity region is reduced, and the contact resistance is reduced”).
In regards to dependent claim 10, Tsuchiya teaches wherein the semiconductor device comprises a Schottky diode and/or a metal-oxide semiconductor field effect transistor (Tsuchiya, [0004]).
In regards to dependent claim 12, Tsuchiya teaches wherein annealing the layer of nickel silicide and the first layer comprises annealing the layer of nickel silicide at an anneal temperature greater than about 800 C (Tsuchiya, [0104]).
In regards to dependent claim 13, Tsuchiya teaches wherein the anneal temperature is between about 825 C and 925 C (Tsuchiya, [0104]).
In regards to dependent claim 14, Tsuchiya teaches wherein the first conductivity type is n-type and wherein the second conductivity type is p-type (Tsuchiya, Fig. 1, 14 vs 16).
In regards to dependent claim 15, Tsuchiya teaches wherein the first layer has a doping concentration of less than about 2E16 cm-3 (Tsuchiya, [0032]).
In regards to dependent claim 16, Tsuchiya teaches wherein the doped region has a doping concentration greater than about 2E19 cm-3 (Tsuchiya, [0035]).
In regards to dependent claim 17, Tsuchiya teaches wherein forming the layer of nickel silicide on the first layer comprises forming a layer of nickel on the first layer and annealing the layer of nickel to form nickel silicide (Tsuchiya, Fig. 6-Fig. 7).
In regards to dependent claim 18, Tsuchiya teaches wherein the layer of nickel is annealed to form nickel silicide at a lower temperature than the layer of nickel silicide is annealed to form the ohmic contact to the doped region and the Schottky barrier junction to the first layer (Tsuchiya, [0098], “a metallic film 36 is formed…More specifically, for example, a nickel film is deposited using sputtering method and the like”, [0104], “two-step annealing method is also effective as a method for forming the nickel silicide layer 18. In this case, silicide is formed at a relatively low temperature of about 700 degrees or less as the first step annealing process then the second step annealing process is performed at a temperature higher than that of the first step annealing process after the unreacted Ni removing process with acid solution. When this is done, the contact resistance can be further reduced,”).
In regards to dependent claim 20, Tsuchiya teaches wherein the first layer has a doping concentration of less than about 2E16 cm-3 (Tsuchiya, [0032]).
In regards to dependent claim 21, Tsuchiya teaches wherein the plurality of doped regions have a doping concentration greater than about 2E19 cm-3 (Tsuchiya, [0035]).
In regards to dependent claim 22, Tsuchiya teaches wherein the semiconductor device comprises a Schottky diode and/or a metal-oxide semiconductor field effect transistor (Tsuchiya, [0004]).
Dependent Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiya.
In regards to dependent claim 23, Tsuchiya fails to explicitly teach wherein the ohmic junctions to the plurality of doped regions have resistivities of about 2 mohm-cm2 or less. However, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
In regards to dependent claim 24, Tsuchiya fails to explicitly teach the Schottky barrier junction to the silicon carbide layer has a barrier height of between about 1.4 eV and 1.7 eV. However, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
In regards to dependent claim 25, Tsuchiya fails to explicitly teach wherein the Schottky barrier junction to the silicon carbide layer has an ideality factor of about 1.15 or less. However, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812