Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Response to Election/Restriction filed on 5/22/2026. Claims 1-20 are pending, wherein claims 14-17 are withdrawn from further consideration as being directed to non-elected invention with traverse as indicated below.
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-13,18-20 in the reply filed on 5/22/2026 is acknowledged. The traversal is on the ground(s) that there is no undue burden on the Examiner to examine the claims of group II along with the claims of group I. This is not found persuasive because (1) Applicant has not provided reasons for undue burdens; (2) the group II further requires the particular logic circuits not found in the group I invention such as the plurality of sticky registers, the detection circuitry, the status register, the assertion-enabled circuitry and the readback circuitry; (3) there is no synthesis of the circuit design that includes assert statement that specifies a conditional expression to be checked during simulation, resulting in a netlist which is then used for placement and routing, as required by group I invention. At best, the group II invention contains the specific hardware circuit for evaluating assert statements in a circuit design, which are different from the computer-implemented method/system of group I invention which performs the synthesis, routing and placement. Accordingly, separate and different searches would be required for invention I and invention II due the different limitations of the claims as previously discussed and discussed above, and a comprehensive search for each invention would require searches in various databases such as USPAT, USPGPUB, EPO, JPO, IBM TDB, Derwent and GOOGLE, resulting in enormous burdens to the Examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claims 12-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/22/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,11,18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Garg et al. (US Patent No. 7,810,056 B1) in view of Deshpande et al. (US Patent No.10,726,182 B1).
As per claims 1,18, Garg et al. disclose the synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist by a design tool as summarized in col. 1, line 45 to col. 2, line 31; wherein the "assertion synthesis of circuitry... to reduce a number of states in a state machine that represents the circuitry" corresponds to synthesizing circuit designs modeled via underlying state/RTL transitions (i.e., the state machine comprises a plurality of sequential elements and combinational logic elements configured to monitor the signals of the circuit design—col. 6, lines 12-29) ; "converting an assertion formula to a sequence implication form... semantically equivalent to the assertion formula" corresponds to the “assertion formula” which represents the conditional/temporal expression dictated by an RTL assert statement; and "synthesizing the resulting formula to the state machine using context aware sequence synthesis" corresponds to the compilation of the assertion formula into a structural state machine (which is represented at the gate/netlist level as flip-flops and combinational logic); and "verifying the circuitry using the state machine” corresponds to the synthesized hardware state machine is actively utilized to verify the circuit's state behavior (see also col. 5, lines 41-47); wherein the one or more processors, memory arrangement are part of the computer system as illustrated in Fig. 6 (see also col. 10, line 5 to col. 10, line 50) . However, Garg et al. failed to further teach placing and routing the netlist into a circuit design layout by the design tool and generating implementation data from the layout by the design tool. Such placement and routing the netlist in the circuit design layout resulting from the final FSM is known in the art and is further taught by Deshpande et al. (see Fig. 1, i.e., block 116 resulted in final FSM, from which block 118 performed the placement and routing, and generating the implementation data; see also col. 4, lines 37-46; col. 8, lines `6-18). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention to further incorporate the teachings of Deshpande et al. into the method/system of Garg et al. because such incorporation would further allow the synthesized netlist of Garg et al. (i.e., as represented by the final FSM) to be placed and routed, from which implementation data is outputted for fabricating the integrated circuit as is known in the art and further taught by Deshpande et al..
As per claims 2, Garg et al. in view of Deshpande et al. teach all of the elements of claim 1, from which the claim depends as discussed in the rejection of claim 1 above, wherein Garg et al. further teach the synthesizing that includes generating netlist elements that define a status register to capture a logic state of the conditional expression corresponds to synthesizing the final state or trap state of the generated Finite State Machine (FSM) (see col. 8, lines 45-61, i.e., the creation of the specific terminal/trap condition that effectively acts as a status flag to capture and hold a violated logic state, i.e., "The synthesized state machine includes at least one target state corresponding to an assertion violation. When the state machine enters the target state, an error signal is generated... The logic is configured to latch the error signal until a reset is applied."
This shows that the design tool synthesizes a dedicated hardware path where a specific sequential state element (a register bit) changes value to capture the logic state of the assertion expression and dynamically logs that a violation has occurred.).
When a temporal RTL assert expression is compiled using methodology of Garg et al., the tool follows a sequence of specific steps to generate those physical register elements:
1. FSM State Mapping into Storage Elements (Flip-Flops)
An assertion checks conditions over time (e.g., "If Request goes high, Acknowledge must follow within 3 cycles"). To keep track of where the system is within this sequence, the tool converts the optimized assertion formula into an FSM.
During the structural synthesis phase, the abstract states of this FSM are mapped to physical sequential netlist elements (D-type Flip-Flops or registers).
2. The "Error" or "Trap" State Register
To act as a status register that captures the pass/fail or trigger state of the conditional expression:
The tool designates a specific state in the FSM as a trap state (often labeled an error or violation state).
The netlist element (the flip-flop) allocated to this trap state acts explicitly as a status flag.
Once the sequential conditional expression violates the assertion rule, the logic transitions into this state, driving the corresponding register to a high logic level.
As per claims 3,11,19, Garg et al. in view of Deshpande et al. teach all of the elements of claims 1 and 18, from which the respective claims depend as discussed in the rejection of claims 1 and 18 above, wherein Garg et al. further teach the synthesizing that includes generating netlist elements that define a sticky register to capture a logic state of the conditional expression corresponds to the feedback loop in the netlist driving the register. That is, it synthesizes a small combinational network (typically an OR gate feeding the D-input of the state flip-flop, paired with its own output) so that once the conditional expression evaluates to an invalid state, the register becomes "sticky"—latching the error permanently until an explicit reset signal clears it (see col. 8, lines 48-62, i.e., the synthesized state machine includes at least one target state corresponding to an assertion violation. When the state machine enters the target state, an error signal is generated... The logic is configured to latch the error signal until a reset is applied.").
Claim(s) 4-10,12-13,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Garg et al. (US Patent No. 7,810,056 B1) in view of Deshpande et al. (US Patent No.10,726,182 B1) and Raynaud et al. (US Patent Application Publication No. 20010011212 A1).
As per claims 4-5, Garg et al. in view of Deshpande et al. teach all of the elements of claims 1 and 18, from which the respective claims depend as discussed in the rejection of claims 1 and 18 above, wherein while Garg et al. covers synthesizing netlist elements for multiple assertions (see col. 2, lines 36-40, i.e., batch parsing; 5, lines 48-56, i.e., batch parsing; col. 6, lines 62-67, i.e., processing a plurality of assertions); Garg et al. in view of Deshpande et al. fail teach generating a map file that specifies for each assert statement an associated bit position in the status register, including line numbers for the plurality of assert statements. Such mapping file is further taught by Raynaud et al. to allow for user interactive simulation and design of the circuit at several breakpoints under various conditions (see paragraphs [0008-[0009], [0011]-[0016], [0083]).
As per claim 6, Garg et al. in view of Deshpande et al. teach all of the elements of claim 1, from which the respective claims depend as discussed in the rejection of claims 1 above, wherein Garg et al. further teach the generation of netlist that define a sticky register to capture a logic state of the conditional expression (see rejections of claims 3,11, and 19 above) but failed to teach this netlist generation applied to sticky registers enabled by several frequencies (i.e., first and second frequencies, including a maximum frequency). Such generating of netlist for monitoring/sampling at multi-clock frequencies including maximum or higher frequency is further taught by Raynaud et al. to allow interactive simulation of the circuit design (see paragraphs [0011]-[0016]; [0091]-[0092).
As per claims 7-10,20, Garg et al. in view of Deshpande et al. teach all of the elements of claims 1 and 18, from which the respective claims depend as discussed in the rejection of claims 1 and 18 above, but failed to teach enabling synthesizing of the assert statement(s) in response to a switch input to the design tool or a first state of the control signal; and bypassing synthesizing of the assert statement(s) in response to absence of the switch input to the design tool or a second state of the control signal. Such enabling/disabling of assert statement(s) is taught by Raynaud et al. to allow interactive simulation of the circuit design (see paragraphs [0011]-[0016]). It would have been obvious to one of ordinary skilled in the art at the effective filing date of the invention to further incorporate the teachings of Raynaud et al. into the method/system of Garg et al. in view of Deshpande et al. because such incorporation would further allow user interactive simulation of the circuit design as further taught by Raynaud et al..
As per claims 12-13¸ Garg et al. in view of Deshpande et al. teach all of the elements of claim 1, from which the claims depend as discussed in the rejection of claims 1 above, wherein Deshpande et al. further teach the programmable integrated circuit configured according to the implementation data (col. 4, lines 37-46). However, Garg et al. in view of Deshpande et al. failed to teach polling a status register indicating a logic state of the conditional expression by the design tool; and displaying data that identify the assert statement based on the status register. Such polling the status register and displaying the corresponding data is further taught by Raynaud et al. to allow for user interactive simulation and design of the circuit (see paragraphs [0013]-[0016]). It would have been obvious to one of ordinary skilled in the art at the effective filing date of the invention to further incorporate the teachings of Raynaud et al. into the method/system of Garg et al. in view of Deshpande et al. because such incorporation would further allow user interactive simulation of the circuit design as further taught by Raynaud et al..
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 August 8, 2026
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