Prosecution Insights
Last updated: July 17, 2026
Application No. 18/211,655

MEMORY DEVICE AND FORMING METHOD THEREOF

Non-Final OA §103
Filed
Jun 20, 2023
Examiner
TRAPANESE, WILLIAM C
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
2 (Non-Final)
77%
Grant Probability
Favorable
2-3
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
493 granted / 640 resolved
+9.0% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
25 currently pending
Career history
667
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
78.2%
+38.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments filed 03/06/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Zhang. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (hereinafter Lin, US 2022/0051940) in view of Zhang et al. (hereinafter Zhang, US 2015/0325467). In regards to independent claim 1, Lin teaches a memory device, comprising: a gate structure on a substrate (Lin, Fig. 8, 208); a source/drain region in the substrate (Lin, Fig. 8, 206); a dielectric layer covering the substrate and the gate structure (Lin, Fig. 8, 220); and a cell contact adjacent to the gate structure (Lin, Fig. 8, 222), wherein the cell contact comprises: a conductive layer (Lin, Fig. 11, 236); a first barrier layer on a sidewall of the conductive layer (Lin, Fig. 11, 224); and a second barrier layer on a bottom surface of the conductive layer (Lin, Fig. 7, 226), wherein the second barrier layer directly contacts the first barrier layer and the source/drain region (Lin, Fig. 7, 226 touch 206 and 224), and a second resistivity of the second barrier layer is lower than a first resistivity of the first barrier layer (Lin, Fig. 11, 226 is Ti/TiN [0025] vs 224 SiN [0021]). Lin does not explicitly teach that wherein a first compactness of the first barrier layer is higher than a second compactness of the second barrier layer. Zhang teaches wherein a first compactness of the first barrier layer is higher than a second compactness of the second barrier layer (Zhang teaches that the sidewall liner 68 can be Tantalum ([0022]) and that the liner that lines the bottom of the contact can be Ruthenium ([0025]), Tantalum has higher density and higher resistivity, while Ruthenium has lower density and lower resistivity). It would have been obvious to one of ordinary skill in the art, having the teachings of Lin and Zhang before him before the effective filing date of the claimed invention, to modify the SiN barrier layer taught by Lin to include the Ta liner of Zhang in order to obtain a barrier layer made of Ta. One would have been motivated to make such a combination because enables the contact to have a lower resistivity by using a conductor as a liner. In regards to dependent claim 2, Lin teaches wherein the first barrier layer and the second barrier layer collectively surround the conductive layer to separate the conductive layer from the dielectric layer and the substrate (Lin, Fig. 11, Item 220, vs Item 224). In regards to dependent claim 4, Lin teaches wherein a first thickness of the first barrier layer is equal to a second thickness of the second barrier layer. However, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). In regards to dependent claim 5, Lin teaches wherein a first thickness of the first barrier layer is smaller than or equal to 20 nm (Lin, [0021]). In regards to dependent claim 6, Lin teaches wherein the first barrier layer and the second barrier layer comprise a same composition (Lin, [0025], nitride). In regards to dependent claim 7, Lin teaches wherein the first barrier layer comprises TiN, SiN, SiO2, or combinations thereof (Lin, SiN). In regards to dependent claim 8, Lin teaches a third barrier layer on a top surface of the dielectric layer, wherein the conductive layer extends onto the third barrier layer, and a third resistivity of the third barrier layer is lower than the first resistivity of the first barrier layer (Lin, 228, [0025]). In regards to dependent claim 9, Lin teaches wherein the third barrier layer directly contacts the first barrier layer (Lin, 234 covers 224, [0025]). In regards to dependent claim 10, Lin teaches wherein a side surface of the third barrier layer is coplanar with a side surface of the first barrier layer (Lin, Fig. 9, 228 and 224). In regards to dependent claim 11, Lin teaches wherein the third resistivity of the third barrier layer is equal to the second resistivity of the second barrier layer (Lin, 228, [0025]). In regards to dependent claim 12, Lin teaches wherein the first barrier layer extends into the source/drain region, and wherein the second barrier layer is lower than a top surface of the substrate (Lin, 224). In regards to dependent claim 13, Lin teaches wherein the first barrier layer comprises a material different from that of the dielectric layer (Lin, SiN vs SiO, [0019]). In regards to independent claim 14, Lin teaches a method of forming a memory device, comprising: providing a gate structure on a substrate and a dielectric layer covering the gate structure (Lin, Fig. 8, 208, 220, [0016]); forming an opening through the dielectric layer, wherein the opening exposes a source/drain region in the substrate (Lin, Fig. 11, 236, [0020]); depositing a first barrier layer in the opening and on the dielectric layer by a first process (Lin, Fig. 11, 224 [0021]); removing a first portion of the first barrier layer on a bottom surface of the opening, wherein a second portion of the first barrier layer is remained on a side surface of the opening (Lin, Fig. 5 [0022}); depositing a second barrier layer on the bottom surface of the opening by a second process, wherein the second barrier layer has a second resistivity different from a first resistivity of the first barrier layer (Lin, Fig. 11, 226 is Ti/TiN [0025] vs 224 SiN [0021], [0024]); and forming a conductive layer in the opening (Lin, [0029]). Lin does not explicitly teach that wherein a first compactness of the first barrier layer is higher than a second compactness of the second barrier layer. Zhang teaches wherein a first compactness of the first barrier layer is higher than a second compactness of the second barrier layer (Zhang teaches that the sidewall liner 68 can be Tantalum ([0022]) and that the liner that lines the bottom of the contact can be Ruthenium ([0025]), Tantalum has higher density and higher resistivity, while Ruthenium has lower density and lower resistivity). It would have been obvious to one of ordinary skill in the art, having the teachings of Lin and Zhang before him before the effective filing date of the claimed invention, to modify the SiN barrier layer taught by Lin to include the Ta liner of Zhang in order to obtain a barrier layer made of Ta. One would have been motivated to make such a combination because enables the contact to have a lower resistivity by using a conductor as a liner. In regards to dependent claim 15, Lin fails to teach wherein the first process is advanced sequential flow deposition, and the second process is chemical vapor deposition. Examiner is taking official notice that ASFD and CVD are two well known methods for depositing thin films to get different step coverage. It would have been obvious to one of ordinary skill in the art, having the teachings of Lin and Official Notice before him before the effective filing date of the claimed invention, to modify the contact barrier layers taught by Lin to include tow forms of deposition of Official Notice in order to obtain a contact with barrier layers deposited by ASFD and CVD. One would have been motivated to make such a combination because it enables one film to have better sidewall coverage while the other film to have better trench deposition. In regards to dependent claim 16, Lin fails to teach wherein the first barrier layer deposited by the first process has the first compactness different from the second compactness of the second barrier layer deposited by the second process. However, it would have been an obvious matter of design choice bounded by well- known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). In regards to dependent claim 17, Lin teaches wherein removing the first barrier layer further comprises removing a third portion of the first barrier layer on a top surface of the dielectric layer (Lin, Fig. 4 vs Fig. 5, Item 224). In regards to dependent claim 18, Lin teaches wherein depositing the second barrier layer on the bottom surface of the opening comprises directly depositing the second barrier layer onto the source/drain region exposed by the opening (Lin, Fig. 5 vs Fig. 6). In regards to dependent claim 19, Lin teaches wherein after depositing the second barrier layer, the first barrier layer and the second barrier layer collectively cover the side surface and the bottom surface of the opening (Lin, Fig. 6). In regards to dependent claim 20, Lin teaches wherein after depositing the second barrier layer, the first barrier layer is exposed in the opening (Lin, Fig. 9). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jun 20, 2023
Application Filed
Jan 08, 2026
Non-Final Rejection mailed — §103
Mar 06, 2026
Response Filed
Jun 17, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

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