Office Action Predictor
Last updated: April 17, 2026
Application No. 18/212,094

DISPLAY DEVICE

Final Rejection §102§103§112
Filed
Jun 20, 2023
Examiner
DYKES, LAURA M
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
samsung display Co. Ltd.
OA Round
2 (Final)
65%
Grant Probability
Moderate
3-4
OA Rounds
2y 10m
To Grant
92%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allow Rate
321 granted / 497 resolved
-3.4% vs TC avg
Strong +28% interview lift
Without
With
+27.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
42 currently pending
Career history
539
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 497 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This OA is in response to the amendment filled on 1/26/2026 that has been entered, wherein claims 1-20 are pending. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 9/27/2022. It is noted, however, that applicant has not filed a certified copy of the 10-2022-0122077 application as required by 37 CFR 1.55. Specification The objection to the specification is withdrawn in light of Applicant’s amendment of 1/26/26. Claim Rejections - 35 USC § 112 The rejection of claims 1-20 under 35 USC 112 is withdrawn in light of Applicant’s amendment of 1/26/2026. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 8-12 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuan et al. (US 2020/0312886 A1). Regarding claim 1, Yuan teaches a display device(Fig. 15) comprising: a display panel(Fig. 12), in which a display region(100) and a non-display region(200, Fig. 12) are defined, wherein the display panel(Fig. 12) includes a base layer(10) including a front surface and a rear surface opposing the front surface, a circuit layer(30, ¶0043) including pixel circuits(31, ¶0043) disposed on the front surface, wherein each pixel circuit(31, ¶0043) includes semiconductor patterns(31c, ¶0047) and conductive patterns(31g, ¶0047) , a light emitting device layer(50, ¶0057) including light emitting devices(51, ¶0057) connected to corresponding pixel circuits(31, ¶0043) of the pixel circuits(31, ¶0043), and display pads(41, ¶0044) connected to the corresponding pixel circuits(31, ¶0043) and exposed to the rear surface of the base layer(10) and disposed in a display pad region on the rear surface of the base layer(10) overlapping the display region(100); and a circuit board(FPC, ¶0090) disposed on the rear surface of the base layer(10) overlapping the display region(100) and bonded to the rear surface at the display pad region and including substrate pads(42, ¶0090) connected to the display pads(41, ¶0044) , wherein the display pads(41, ¶0044) and the substrate pads(42, ¶0090) are bonded to each other on the rear surface, wherein a first display pad(please see examiner annotated Fig. 2) and a second display pad(please see examiner annotated Fig. 2), which are adjacent to each other, of the display pads(41, ¶0044) overlap corresponding semiconductor patterns(31c, ¶0047) of the semiconductor patterns(31c, ¶0047) and corresponding conductive patterns(31g, ¶0047) of the conductive patterns(31g, ¶0047) with a substantially same overlapping region as each other(there is no evidence that the first and second display pads are not substantially same as each other). PNG media_image1.png 333 628 media_image1.png Greyscale Regarding claim 8, Yuan teaches the display device of claim 1, wherein the first display pad((please see examiner annotated Fig. 2) and the second display pad(please see examiner annotated Fig. 2) defines a pad group(B, Fig. 2, ¶0050), and wherein the pad group(B, Fig. 2, ¶0050) is provided in plural(¶0050), and a plurality of pad groups(B, Fig. 2, ¶0050) is spaced apart from each other in one direction(¶0050). Regarding claim 9, Yuan teaches the display device of claim 1, wherein the first display pad((please see examiner annotated Fig. 2) and the second display pad(please see examiner annotated Fig. 2) have a same area as each other(please see examiner annotated Fig. 2). Regarding claim 10, Yuan teaches the display device of claim 1, wherein the first display pad((please see examiner annotated Fig. 2) and the second display pad(please see examiner annotated Fig. 2) have a same shape as each other(please see examiner annotated Fig. 2). Regarding claim 11, Yuan teaches the display device of claim 1, wherein the circuit layer(30, ¶0043) includes a plurality of insulating layers(unlabeled gate insulating layer and interlayer layers between 31c, 31g and 51 in Fig. 15) , and wherein the semiconductor patterns(31c, ¶0047) and the conductive patterns(31g, ¶0047) are interposed between the insulating layers(unlabeled gate insulating layer and interlayer layers between 31c, 31g and 51 in Fig. 15). Regarding claim 12, Yuan teaches the display device of claim 1, further comprising: a lower film(60, ¶0090) interposed between the display panel(Fig. 12) and the circuit board(FPC, ¶0090), wherein a portion of the circuit board(FPC, ¶0090) is disposed on a rear surface of the lower film(60, ¶0090). Regarding claim 17, Yuan teaches a display device(Fig. 15) comprising: a base layer(10) including a front surface, on which a display region(100) and a non- display region(100) are defined, and a rear surface opposing the front surface; a pixel(31, 21, 51) disposed on the front surface of the base layer(10), where the pixel(31, 21, 51) includes a pixel circuit(31, ¶0043) including semiconductor patterns(31c, ¶0047) and conductive patterns(21, ¶0047) and a light emitting device(51, ¶0057) connected to the pixel circuit(31, ¶0043); a display pad(41, ¶0044) connected to the pixel circuit(31, ¶0043) and exposed to the rear surface of the base layer(10) overlapping the display region(100) and disposed in a display pad region on the rear surface of the base layer(10); and a circuit board(FPC, ¶0090) facing the rear surface of the base layer(10) overlapping the display region(100) and bonded to the rear surface at the display pad region and including substrate pads(42, ¶0090), wherein the display pad(41, ¶0044) is provided in plural, wherein each of the substrate pads(42, ¶0090) is connected to a corresponding display pad(41, ¶0044) of display pads(41, ¶0044) and the display pads(41, ¶0044) and the substrate pads(42, ¶0090) are bonded to each other on the rear surface, wherein a first display pad(please see examiner annotated Fig. 2) and a second display pad(please see examiner annotated Fig. 2), which are adjacent to each other, of the display pads(41, ¶0044) overlap the pixel circuit(31, ¶0043) with a substantially same overlapping area as each other(there is no evidence that the first and second display pads are not substantially same as each other). Regarding claim 18, Yuan teaches the display device of claim 17, wherein the pixel(31, 21, 51) includes: each of at least one transistor(31, ¶0047) including an active pattern(31c, ¶0047), which is defined by a portion of the semiconductor patterns(31c, ¶0047) , and a gate(31g, ¶0047) overlapping the active pattern(31c, ¶0047), and wherein the at least one transistor(31, ¶0047) is connected to the light emitting device(51, ¶0057). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US 2020/0312886 A1). Regarding claim 2, Yuan teaches the display device of claim 1. Yuan does not explicitly state regions, in which the first display pad(please see examiner annotated Fig. 2) overlaps the pixel circuits(31, ¶0043), are symmetrical with regions, in which the second display pad(please see examiner annotated Fig. 2) overlaps the pixel circuits(31, ¶0043). However the use of symmetry is a well-known design choice. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make regions, in which the first display pad overlaps the pixel circuits, are symmetrical with regions, in which the second display pad overlaps the pixel circuits, in order to make the first and second display pad aesthetically pleasing. Regarding claim 20, Yuan teaches the display device of claim 17. Yuan does not explicitly state regions, in which the first display pad(please see examiner annotated Fig. 2) overlaps the pixel circuit, are symmetrical with regions in which the second display pad(please see examiner annotated Fig. 2) overlaps the pixel circuit. However the use of symmetry is a well-known design choice. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make regions, in which the first display pad overlaps the pixel circuits, are symmetrical with regions, in which the second display pad overlaps the pixel circuits, in order to make the first and second display pad aesthetically pleasing. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US 2020/0312886 A1) in view of Kim et al. (US 2022/0093649 A1). Regarding claim 13, Yuan teaches the display device of claim 1, but is not relied on to teach the display pads(41, ¶0044) and the substrate pads(42, ¶0090) are connected to each other through an anisotropic conductive film. Kim teaches a display device(Fig. 3A) wherein the display pads(PAD, ¶0104) and the substrate pads(30, ¶0104) are connected to each other through an anisotropic conductive film(ACF, ¶0104). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yuan, so that the display pads and the substrate pads are connected to each other through an anisotropic conductive film, as taught by Kim, in order for the display pads to physically and electrically connected to the substrate pads(¶0104). Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US 2020/0312886 A1) in view of Yim et al. (US 2022/019958 A1) of record. Regarding claim 14, Yuan teaches the display device of claim 1, but is not relied on to teach an input sensor directly disposed on the display panel(Fig. 12), and including at least one conductive layer and at least one sensing insulating layer. Yim teaches an display device(Fig. 5) comprising an input sensor(ISP, ¶0130) directly disposed on the display panel(DP-OLED, ¶0109), and including at least one conductive layer(first and second conductive layer, not shown, ¶0127) and at least one sensing insulating layer(SIL, ¶0127). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yuan to include an input sensor directly disposed on the display panel, and including at least one conductive layer and at least one sensing insulating layer, as taught by Yim, so that the display device can sense an external input and/or an external pressure(¶0060). Regarding claim 15, Yuan teaches the display device of claim 14, but is not relied on to teach an anti-reflective layer disposed on the input sensor. Yim teaches an display device(Fig. 5) comprising an anti-reflective layer(RPL, ¶0084) disposed on the input sensor(ISP, ¶0130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yuan, to include an anti-reflective layer disposed on the input sensor, as taught by Yim, in order to reduce a reflectance of external light incident thereto from above the window(¶0083). Regarding claim 16, Yuan teaches the display device of claim 15, but is not relied on to teach a window disposed on the anti-reflective layer, wherein the window includes a base substrate, and a bezel pattern disposed on a bottom surface of the base substrate and overlapping the non-display region(200, Fig. 12). Yim teaches an display device(Fig. 5) comprising a window(WM, ¶0059) disposed on the anti-reflective layer(RPL, ¶0084), wherein the window(WM, ¶0078) includes a base substrate(¶0059), and a bezel pattern(SHP_a, ¶0078) disposed on a bottom surface of the base substrate and overlapping the non-display region(TA, ¶0078). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yuan, to include a window disposed on the anti-reflective layer, wherein the window includes a base substrate, and a bezel pattern disposed on a bottom surface of the base substrate and overlapping the non-display region, as taught by Yim, in order to prevent the edge of the electronic optical module from being perceived by a user(¶0079). control Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US 2020/0312886 A1) in view of Chen et al. (US 2022/0121072 A1) of record. Regarding claim 19, Yuan teaches the display device of claim 18, further comprising: a signal line(21, ¶0047) connected to the pixel(31, 21, 51) and defined by a portion of the conductive patterns(21, ¶0047), wherein the signal line(21, ¶0047) includes data lines(data lines, ¶0047), and a power line(21, ¶0047). Yuan is not relied on to teach the signal line(21, ¶0047) include scan lines, light emitting lines and control lines. Chen teaches a display device(Fig. 3) wherein the signal line includes scan lines(111, ¶0076), light emitting lines(¶0079) and control lines(110, ¶0080). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee, so that the signal line includes include scan lines, light emitting lines and control lines(, as taught by Chen, in order to turn on the TFT and pixel electrode(¶0077) and to transmit light emitting control signals(¶0079). Allowable Subject Matter Claims 3-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Please see the OA dated 11/4/2025 for reasons for indicating allowable subject matter. Response to Arguments Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAURA M DYKES/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jun 20, 2023
Application Filed
Oct 31, 2025
Non-Final Rejection — §102, §103, §112
Dec 30, 2025
Interview Requested
Jan 08, 2026
Examiner Interview Summary
Jan 08, 2026
Applicant Interview (Telephonic)
Jan 26, 2026
Response Filed
Feb 10, 2026
Final Rejection — §102, §103, §112
Apr 15, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
65%
Grant Probability
92%
With Interview (+27.9%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 497 resolved cases by this examiner. Grant probability derived from career allow rate.

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