Prosecution Insights
Last updated: April 19, 2026
Application No. 18/212,155

ELECTRONIC DEVICE

Non-Final OA §102
Filed
Jun 20, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1493 granted / 1633 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1671
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
39.9%
-0.1% vs TC avg
§102
41.8%
+1.8% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1633 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-20 in the reply filed on 11/13/25 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US pub 20220359324). With respect to claim 1, Lin et al. teach an electronic device, comprising: a package structure comprising (see figs. 1-4, particularly fig. 2C, para 0047, 0048 and associated text): an electronic component 21; a plurality of first conductive structures 212, 210a connected to the electronic component; and an encapsulant 25 encapsulating the electronic component and exposing a portion of the plurality of first conductive structures; and a power regulating component 24 comprising a plurality of second conductive structures (conductors directly above 212,210a) directly bonded with the plurality of first conductive structures and configured to provide the electronic component with a power signal. With respect to claim 2, Lin et al. teach the electronic component has an active surface and a backside surface (upper surface) opposite to the active surface, and the backside surface of the electronic component is configured to allow power signal to pass through. See fig. 2C and associated text and para 0047,0048. Claim(s) 12 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US pub 20220359324). With respect to claim 12, Lin et al. teach an electronic device, comprising: a package structure comprising (see figs. 1-4, particularly fig. 2C, para 0047, 0048 and associated text): a package structure comprising an encapsulant 25, an electronic component 21 encapsulated by the encapsulant, and a first conductive element 212, 210a exposed by the encapsulant; and an integrated circuit 24 vertically on the package structure and comprising a second conductive element (conductors directly above 212,210a) connected to the first conductive element through a non-solder joint. With respect to claim 17, Lin et al. teach the electronic component has a first surface (bottom) connected to a circuit structure 7 through a solder-joint 29 and a second surface (top) opposite to the first surface and facing the integrated circuit. See fig. 2E-1 and associated text. Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US pub 20220359324). With respect to claim 18, Lin et al. teach an electronic device, comprising: a package structure comprising (see figs. 1-4, particularly fig. 2C, para 0047, 0048 and associated text): a package structure comprising: an electronic component 21; a first conductive structure 212, 210a disposed over the electronic component; and a second conductive structure 23 disposed adjacent to a lateral surface of the electronic component; and PNG media_image1.png 6 2 media_image1.png Greyscale a second electronic component 24 comprising a plurality of third conductive structures (conductors directly above 212,210a) directly connected to the first conductive structure and the second conductive structure. With respect to claim 20, Lin et al. teach a top surface of the first conductive structure is substantially aligned with a top surface of the second conductive structure. See fig. 2C and associated text and para 0047,0048. Allowable Subject Matter Claims 3-11, 13-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a encapsulated component and an exposed conductor and an IC over the structure having a conductor directly connected to the exposed conductor as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 20, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604733
PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604754
PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604766
SEMICONDUCTOR PACKAGE STRUCTURE
2y 5m to grant Granted Apr 14, 2026
Patent 12604739
Semiconductor Device and Method of Forming a 3-D Stacked Semiconductor Package Structure
2y 5m to grant Granted Apr 14, 2026
Patent 12599033
QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SERIALIZER/DESERIALIZER
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.6%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1633 resolved cases by this examiner. Grant probability derived from career allow rate.

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