Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 10/22/25 is acknowledged.
Claims 14-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/22/25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US Patent 7,297,609).
Claim 1: Kim teaches (Fig. 2A) a method, comprising: forming a front side oxide layer (201) and a back side oxide layer (201) on a first substrate (200); depositing a front side nitride layer (207) on the front side oxide layer and a back side nitride layer (207 )on the back side nitride layer; forming an enhancing layer (204) on the back side nitride layer; and performing a process sequence to fabricate a circuitry structure on the front side nitride layer (Fig. 2C-2D). The claim does not specific what the circuitry structure is. Kim teaches isolation structures to isolate the active regions of the device. These isolation structures can be considered a “circuitry structure” or the fact that there are active regions in the device implies more active circuitry structures such as transistors and their associated interconnections. Additionally, subsequent copper formation indicates the addition of circuitry structures being added to the device.
Claim 10: Kim teaches a method for modulating warpage, comprising: providing a first substrate (200) , wherein the first substrate has a front surface and a back surface; depositing a back side film stack (201, 207, 204)on the back surface to create a positive warpage profile in the first substrate; and bonding the front surface of the first substrate to a second substrate or electrical connectors. Kim teaches the addition of active regions and copper line formation which implies electrical connections.
Claim 11: Kim teaches (Fig. 2A-2E) depositing the back side film stack comprises: forming a front side oxide layer (201) and a back side oxide layer (201)on the first substrate; depositing a front side nitride layer (207) on the front side oxide layer and a back side nitride layer (207) on the back side nitride layer; and forming a front side enhancing layer (2) over the front side nitride layer and a back side enhancing layer (204) on the back side nitride layer.
Claim 12: Kim teaches (Fig. 2E-2F) removing the front side enhancing layer.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Terahara (US PGPub 2009/0197355).
Claim 1: Terahara teaches a method, comprising: forming a front side oxide layer (2a) and a back side oxide layer (2b) on a first substrate (1); depositing a front side nitride layer (3a) on the front side oxide layer and a back side nitride layer (3b) on the back side nitride layer; forming an enhancing layer (4b) on the back side nitride layer; and performing a process sequence to fabricate a circuitry structure on the front side nitride layer [0055].
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kubota et al. (US PGPub 2025/0198049).
Claim 10: Kubota teaches a method for modulating warpage, comprising: providing a first substrate (3) , wherein the first substrate has a front surface and a back surface; depositing a back side film stack [0060] on the back surface to create a positive warpage profile in the first substrate; and bonding the front surface of the first substrate to a second substrate (20) or electrical connectors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Patent 7,297,609)
Claim 13: Kim teaches forming a plurality of contact openings through the front side enhancing layer, the front side nitride layer and the front side oxide layer; and forming a plurality of electrical connectors in the plurality of contact openings. The formation of contact openings and subsequent electrical connectors is common in the semiconductor art and therefore one of ordinary skill in the art would know how to manufacture contact openings and electrical connectors within or connected to a substrate through a passivation film on the substrate.
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach bonding a second substrate with the enhancing layer still on and exposed on the backside. The bonding of substrates via passivation/enhancing layers on the same side of the circuitry, but does not show the enhancing layer on the backside during the process. Claims 3-4 depend on claim 2. The prior art of record do not teach the details regarding the enhancing ad etch stop layers details in claims 5-7. Claims 8-9 depend on claims 5 and 6. The prior art of record does not teach the enhancing film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814