DETAILED ACTION
This Office Action is in response to Application filed June 22, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B drawn to the embodiment shown in Fig. 3 of current application, claims 1 and 8-20, in the reply filed on November 30, 2025 is acknowledged.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
On line 1 of claims 1-20, “method for epitaxy of a high electron mobility transistor” recited in the preamble should be amended, because (a) a high electron mobility transistor should also comprise conductive layers such as metal layers for forming a source, drain and gate electrode, which are not formed by “epitaxy”, (b) the claim body of claim 1 is directed to a method for forming an intermediate device structure on the way toward forming “a high electron mobility transistor” rather than a method for forming a complete structure of “a high electron mobility transistor”, (c) this point can also be seen clearly with respect to the limitation “the high electron mobility transistor epitaxial structure” recited in claims 14-16 and 19, i.e. a method for epitaxy of a high electron mobility transistor is one thing, and a method for forming a high electron mobility transistor epitaxial structure is another, and (d) furthermore, Applicant also claims a step of “forming a passivation layer” in claim 13, which may or may not be formed by epitaxy.
On line 2 of claim 14, the term “BOW” should be delineated, because meanings of acronyms can change over time.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claims 14-16 and 19, it is not clear what the limitation “the high electron mobility transistor epitaxial structure” recited on lines 2-3 of claims 14-16 and on line 2 of claim 19 each refers to, because (a) Applicant does not claim “a high electron mobility transistor epitaxial structure” before claiming “the high electron mobility transistor epitaxial structure”, and (b) therefore, the limitation “the high electron mobility transistor epitaxial structure” lacks the antecedent basis.
(2) Regarding claim 14, it is not clear what “the high electron mobility transistor epitaxial structure” recites on lines 2-3 includes, because (a) Applicant does not claim “the high electron mobility transistor epitaxial structure” per se, but rather claims “an absolute value of a BOW”, (b) therefore, depending on what “the high electron mobility transistor epitaxial structure” includes, the claimed “absolute value of a BOW” would vary, (c) for example, it is not clear whether the claimed high electron mobility transistor epitaxial structure also includes the passivation layer recited in claim 13 from which claim 14 does not depend, and (d) if the claimed “absolute value of a BOW” requires the passivation layer recited in claim 13, then claim 14 would be further indefinite since the structure recited in claim 10 from which claim 14 depends would not lead to the claimed “absolute value of a BOW” recited in claim 14.
(3) Further regarding claim 14, it is not clear under which condition(s) “an absolute value of a BOW of the high electron mobility transistor epitaxial structure is less than 30 um”, and what “an absolute value of a BOW of the high electron mobility transistor epitaxial structure” refers to in the first place, because (a) “an absolute value of a BOW of the high electron mobility transistor epitaxial structure” would depend on numerous device and growth parameters, and growth conditions, none of which Applicant claims in claim 14, (b) in paragraph [0031] of current application, Applicant states that “The value of the BOW is a bowing degree of the wafer and a bowing direction of the wafer, wherein a positive BOW value is a degree of the wafer bowing upward, and a negative BOW value is a degree of the wafer bowing downward”, (c) therefore, the claimed “absolute value of a BOW of the high electron mobility transistor epitaxial structure” depends on, for example, a certain temperature and a rate at which the certain temperature changes, neither of which Applicant claims in claim 14, (d) furthermore, it is not clear how “the high electron mobility transistor epitaxial structure” can be defined and measured since a BOW value of a wafer is distinct from a BOW value of an epitaxial structure, which is in turn distinct from a BOW value of a device structure of the high electron mobility transistor, and (e) it is not clear whether the claimed “absolute value of a BOW of the high electron mobility transistor epitaxial structure” is measured after forming only one high electron mobility transistor on the claimed substrate recited on line 2 of claim 1, or measured after singulating or dicing a single high electron mobility transistor from the entirety of the substrate.
(4) Regarding claims 15 and 16, it is not clear what “a (102) face of the high electron mobility transistor epitaxial structure 1 is less than 700 arcsec” recited on lines 2-3 of claim 15, and “a (102) face of the high electron mobility transistor epitaxial structure 1 is less than 600 arcsec” recited on lines 2-3 of claim 16 each refers to, because (a) it appears that Applicant claims that the claimed high electron mobility transistor epitaxial structure has the claimed (102) face, and (b) however, Applicant’s claimed high electron mobility transistor is formed of GaN-based semiconductor materials, see for example, claim 20, which comprise hexagonal or wurtzite lattice structures expressed by four digits for their crystallographic orientations such as (1000), (0001), (1-100), etc. rather than three digits for their crystallographic orientations such as the claimed (102) face.
(5) Regarding claim 17, it is not clear what the limitation “a number of defects with a diameter” recited on line 2 refers to, because (a) it is not clear what “a diameter” of the defects refers to, (b) in other words, it is not clear whether Applicant claims that the defects are spherical defects or planar defects with circular shapes, and (c) furthermore, it is not clear whether claim 17 would be automatically met if the claimed defects are not perfectly spherical or circular since when the claimed defects are not perfectly spherical or circular, there would be no diameters for the defects to begin with.
(6) Regarding claim 18, it is not clear what the limitation of claim 18 suggests, because (a) the claimed length of the longest crack appears to be a crack that may exist in a passivation layer deposited on an entirety of the substrate recited on line 2 of claim 1 rather than a crack inside a passivation layer for the claimed single high electron mobility transistor, and (b) therefore, the limitation of claim 18 would be automatically satisfied when the claimed high electron mobility transistor is less than 3 mm wide.
(7) Regarding claim 19, it is not clear what “a breakdown voltage of the high electron mobility transistor epitaxial structure” recited on line 2 refers to, because (a) as discussed above under 35 USC 112(b) rejections, the limitation “the high electron mobility transistor epitaxial structure” lacks the antecedent basis, (b) for one to measure a breakdown voltage of a device structure, one needs to form at least two contact electrodes on the device structure, (c) however, it is not clear where the at least two contact electrodes should be formed on “the high electron mobility transistor epitaxial structure”, and (d) furthermore, it is not clear whether “the high electron mobility transistor epitaxial structure” includes “a third nitride layer” recited in claim 8 and/or “a passivation layer” recited in claim 13, especially when claim 19 depends on claim 13; in other words, it is not clear whether the at least two contact electrodes for measuring the claimed breakdown voltage would be formed on the passivation layer recited in claim 13, which may not be associated with an operation of the claimed high electron mobility transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0273084)
Regarding claim 1, Chen et al. disclose a method for epitaxy of a high electron mobility transistor (Fig. 1), comprising: providing a substrate (104) ([0016]); forming a nucleation layer (102; rough buffer layer) on the substrate, because atoms constituting the subsequently deposited seed buffer layer 112 nucleates on the rough buffer layer 102; forming a buffer layer (112; seed buffer layer) ([0018]) on the nucleation layer; forming a first nitride layer (116; graded AlGaN buffer layer) ([0025]) on the buffer layer, wherein the first nitride layer is in contact with the buffer layer (112); forming a second nitride layer (118; isolation GaN buffer layer) ([0027]-[0028]) on the first nitride layer (116), and performing carbon doping on the second nitride layer (buffer element of carbon in [0027]), wherein the second nitride layer (118) is in contact with the first nitride layer; forming a channel layer (120) ([0027]) on the second nitride layer; and forming a barrier layer (122) ([0029]) on the channel layer, wherein a two-dimensional electron gas (126) ([0031]) is formed in the channel layer (120) along an interface between the channel layer and the barrier layer.
Chen et al. differ from the claimed invention by not showing that a growth temperature of the second nitride layer is less than a growth temperature of the first nitride layer; a film thickness of the first nitride layer is less than a film thickness of the second nitride layer.
Chen et al. further disclose that a growth temperature of the second nitride layer (118) is about 900-1050 oC (disclosure that “the isolation buffer layer 118 is formed at a process temperature of about 900-1050 degrees Celsius” in [0080]), and a growth temperature of the first nitride layer (116) of about 1000-1150 oC (disclosure that “the graded buffer layer 116 is formed at a process temperature of about 1000-1150 degrees Celsius” in [0078]); in addition, Chen et al. further disclose that a film thickness of the first nitride layer (116) is about 0.5-1.5 micrometers (disclosure that “the graded buffer layer 116 has a thickness Tg of about 0.5-1.5 micrometers in [0077]), and a film thickness of the second nitride layer (118) is about 0.5-2.5 micrometers (disclosure that “a thickness of the isolation buffer layer 118 is about 0.5-2.5 micrometers in [0079]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a growth temperature of the second nitride layer can be less than a growth temperature of the first nitride layer; a film thickness of the first nitride layer can be less than a film thickness of the second nitride layer, because (a) the growth temperature of the second nitride layer 118 disclosed by Chen et al. is about 900-1050 oC, and the growth temperature of the first nitride layer 116 is about 1000-1150 oC, (b) therefore, (i) when the growth temperature of the second nitride layer 118 is, for example, in the range of about 900-1000 oC, which would have been obvious since the range of about 900-1000 oC is within a range of the growth temperature of the second nitride layer 118 disclosed by Chen et al., or (ii) when the growth temperature of the first nitride layer 116 is, for example, in the range of about 1050-1150 oC, which would also have been obvious since the range of about 1050-1150 oC is within a range of the growth temperature of the first nitride layer 116 disclosed by Chen et al., the growth temperature of the second nitride layer 118 would be less than the growth temperature of the first nitride layer 116, (c) also, the film thickness of the first nitride layer 116 disclosed by Chen et al. is about 0.5-1.5 micrometers, and the film thickness of the second nitride layer 118 disclosed by Chen et al. is about 0.5-2.5 micrometers, and (d) therefore, when the film thickness of the second nitride layer 118 is, for example, in the range of about 1.5-2.5 micrometers, which would have been obvious since the range of about 1.5-2.5 micrometers is within a range of the film thickness of the second nitride layer 118 disclosed by Chen et al., the film thickness of the first nitride layer 116 would be less than the film thickness of the second nitride layer 118.
Regarding claims 13 and 17, Chen et al. further comprise forming a passivation layer (128) ([0033]) on the barrier layer (122) (claim 13), wherein a number of defects with a diameter greater than 0.5 um per square centimeter of a surface of the passivation layer is less than 10, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) no defects would be perfectly spherical or circular to have “a diameter” since there are always atomic-scale corrugations in any defects, rendering the limitation recited in claim 17 inherent since zero defects having the claimed feature is less than 10 defects having the claimed feature (claim 17).
Regarding claim 18, Chen et al. differ from the claimed invention by not showing that a length of a longest crack extending inward from an outer peripheral edge of the passivation layer is less than or equal to 3 mm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a length of a longest crack extending inward from an outer peripheral edge of the passivation layer can be less than or equal to 3 mm, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) this limitation would be automatically satisfied when the claimed high electron mobility transistor has a lateral length less than or equal to 3 nm, which would have been obvious to one of ordinary skill in the art since, the smaller the high electron mobility transistor is, the higher the density of the high electron mobility transistors would be, resulting in a lower manufacturing cost.
Regarding claim 19, Chen et al. further disclose for the method for epitaxy of the high electron mobility transistor as claimed in claim 13 that a breakdown voltage of the high electron mobility transistor epitaxial structure is greater than or equal to 0.09 V/nm, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) therefore, the claimed breakdown voltage of the high electron mobility transistor epitaxial structure can be measured at arbitrary points to satisfy the claim limitation of claim 19.
Regarding claim 20, Chen et al. differ from the claimed invention by not showing that the buffer layer is made of aluminum-gallium nitride (AlGaN) and has a surface aluminum (Al) concentration of 25%±10%.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the buffer layer can be made of aluminum-gallium nitride (AlGaN) and has a surface aluminum (Al) concentration of 25%±10%, because (a) the material composition of the seed buffer layer 112 disclosed by Chen et al., which corresponds to the claimed buffer layer, can be selected to reduce the lattice mismatch and strain between the substrate and the semiconductor layers deposited on the seed buffer layer, and (b) therefore, the seed buffer layer 112 disclosed by Chen et al. can be made of AlGaN having the claimed Al concentration to improve the quality of the semiconductor layers deposited on the seed buffer layer 112.
Allowable Subject Matter
Claims 8-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dellas et al. (US 11,508,830)
Cheng et al. (US 11,469,101)
Nakata et al. (US 2012/0025203)
Ishiguro et al. (US 10,431,656)
Suzuki et al. (US 11,476,115)
Wan et al. (US 9,608,075)
Narukawa et al. (US 11,316,018)
Fukazawa et al. (US 10,186,421)
Abe et al. (US 10,068,858)
Yoshida et al. (US 8,785,942)
Hoteida et al. (US 9,111,839)
Ishiguro et al. (US 9,184,241)
Iwami et al. (US 8,860,038)
Shioda et al. (US 8,785,943)
Hikosaka et al. (US 9,391,145)
Hung et al. (US 8,928,000)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 January 30, 2026