Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 28-44 in the reply filed on 11/7/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/23/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 31 objected to because of the following informalities: the claim appears to have a typographical error "The semiconductor device of Claim 31,". For the purpose of examination, the examiner will interpret the above limitation as "The semiconductor device of Claim 30,".
Claim 45 objected to because of the following informalities: the claim appears to have a typographical error " a mesa stripe on the drift region". For the purpose of examination, the examiner will interpret the above limitation as " a mesa stripe on a drift region".
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 41 and 43 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Islam et al. US 2022/0173227.
Re claim 41, Islam teaches a semiconductor device (500, fig5, [96]), comprising:
a substrate (210, fig5, [96]); and
a mesa (220-260, fig5, [74, 96, 99]) on the substrate, the mesa comprising a drift region (220, fig5, [96]), a channel region (278 n-, fig5, [96]) on the drift region, and a source region (260 n++, fig5, [96]) on the channel region, wherein the channel region and the source region have a first conductivity type (n-type, [96]);
wherein the drift region (220, fig5 and 2A, [96]) comprises a superjunction region including a central pillar (530 n+, fig5, [99]) having the first conductivity type and outer pillars (540 P, fig5, [97]) on opposite sides of the central pillar,
wherein the outer pillars have a second conductivity type (p-type, [97]) opposite the first conductivity type (n-type, [96]).
Re claim 43, Islam teaches the semiconductor device of Claim 41, wherein the drift region (220 n-type, fig5, [96]) further comprises a first region (center part of 220 under 530, fig5) beneath the central pillar (530 n+, fig5, [97]) and the outer pillars (540 P, fig5, [99]), the first region having the first conductivity type ([96])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 28-33, 36, 42 and 45-47 are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al. US 2022/0173227 in view of Lichtenwalner et al. US 2023/0087937.
Re claim 28, Islam teaches a semiconductor device (500, fig5, [96]), comprising:
a substrate (210, fig5, [96]); and
an epitaxial structure (220-260, fig5, [74, 96, 99]) on the substrate, the epitaxial structure comprising: a drift region (220, fig5, [96]); and
a mesa stripe (275, fig5, [96]) on the drift region (220, fig5 and 2A, [96]), the mesa stripe comprising a channel region (278, fig5, [96]) on the drift region (220, fig5, [96]), a source region (260 n++, fig5, [96]) on the channel region (278 n-, fig5, [96]), and sidewall gate regions (284, fig5, [98]) on opposite sides of the channel region (278, fig5, [96]),
wherein the channel region (278, fig5, [96]) and the source region (260, fig5, [96]) have a first conductivity type (n-type, [96]) and the sidewall gate regions (284, fig5, [98]);
wherein the drift region (220, fig5 and 2A, [96]) comprises a superjunction region including a central pillar (530 n+, fig5, [99]) having the first conductivity type and outer pillars (540 P, fig5, [97]) on opposite sides of the central pillar, wherein the outer pillars have the second conductivity type.
Islam does not explicitly show the sidewall gate regions have a second conductivity type opposite the first conductivity type.
Lichtenwalner teaches the sidewall gate regions (38 P+, fig5, [56, 69]) have a second conductivity type opposite the first conductivity type channel region (36 N, fig5, [56, 69]);
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Islam and Lichtenwalner to replace the gate structure with P-type sidewall gate regions. The motivation to do so is to achieve better current control of the N channel region (Lichtenwalner, [69]).
Re claim 29, Islam modified above teaches the semiconductor device of Claim 28, wherein the drift region (220, fig5, [96]) further comprises a first region (center part of n-type 220 under 530, fig5) beneath the central pillar (530 n+, fig5, [99]) and the outer pillars (540 P, fig5, [97]), the first region having the first conductivity type.
Re claim 30, Islam does not explicitly show the semiconductor device of Claim 28, wherein the central pillar and the outer pillars have a height of at least about 2 microns.
Islam teaches fin height H of about 300nm-3µm (275, fig13/14, [80]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the thickness of the shielding region according to the height of the fin. The motivation to do so is to achieve reliability and ruggedness (Islam, [97]) and improve the overall conduction area of the device (Islam, [126]).
Re claim 31, Islam modified above teaches the semiconductor device of Claim 30, wherein the epitaxial structure (220-260, fig5, [74, 96, 99]) comprises a pair of trenches (T, fig13/14, [125]) on opposite sides of the mesa (275, fig5, 13/14, [96]), wherein the outer pillars (540 P, fig5, [97]) are provided beneath respective ones of the trenches.
Re claim 32, Islam modified above teaches the semiconductor device of Claim 28, wherein the sidewall gate regions (284 formed at the foot of each trench, fig5, [98]) are formed beneath respective ones of the trenches (T, fig13/14, [125]).
Re claim 33, Islam modified above teaches the semiconductor device of Claim 28, wherein the semiconductor device comprises a plurality of alternating mesa stripes (275, fig5, 13/14, [96]) and trenches (T, fig13/14, [125]) that extend in a first direction (Y, fig13/14) along the semiconductor substrate and have respective opposing first and second ends, and wherein the alternating mesa stripes and trenches are spaced apart in a second direction (X, fig13/14) that is perpendicular to the first direction (Y, fig13/14).
Re claim 36, Islam modified above teaches the semiconductor device of Claim 33, wherein the third region comprises a doped region that defines an active region of the semiconductor device within the doped region (220 around Fin 275”, fig14) and a termination region (trenches at ends of 275” along Y, fig14) of the semiconductor device outside the doped region.
Re claim 42, Islam modified above teaches the semiconductor device of Claim 41, wherein the mesa further comprises sidewall gate regions (284, fig5, [98]) on opposite sides of the channel region.
Islam does not explicitly show the sidewall gate regions having the second conductivity type.
Lichtenwalner teaches the sidewall gate regions (38 P+, fig5, [56, 69]) have a second conductivity type opposite the first conductivity type channel region (36 N, fig5, [56, 69]);
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Islam and Lichtenwalner to replace the gate structure with P-type sidewall gate regions. The motivation to do so is to achieve better current control of the N channel region (Lichtenwalner, [69]).
Re claim 45, Islam teaches a semiconductor device (500, fig5, [96]), comprising:
a semiconductor region; and
a mesa stripe (220-260, fig5, [74, 96, 99]) on a drift region (220, fig5, [96]), the mesa stripe comprising a first region (275, fig5, [96]) on the drift region, a second region (260 n++, fig5, [96]) on the first region, and sidewall gate regions (284, fig5, [98]) on opposite sides of the first region,
wherein the first region (275 n-, fig5, [77,96]) and the second region (260 n++, fig5, [96]) have a first conductivity type;
wherein the drift region comprises a superjunction region including a central pillar (530 n+, fig5, [99]) having the first conductivity type and outer pillars (540 P, fig5, [97]) on opposite sides of the central pillar, wherein the outer pillars have the second conductivity type.
Islam does not explicitly show the sidewall gate regions have a second conductivity type opposite the first conductivity type.
Lichtenwalner teaches the sidewall gate regions (38 P+, fig5, [56, 69]) have a second conductivity type opposite the first conductivity type channel region (36 N, fig5, [56, 69]);
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Islam and Lichtenwalner to replace the gate structure with P-type sidewall gate regions. The motivation to do so is to achieve better current control of the N channel region (Lichtenwalner, [69]).
Re claim 46, Islam modified above teaches the semiconductor device of Claim 45, wherein the first region (275 n-, fig5, [77,96]) comprises a channel region (278, fig5, [96]) and the second region comprises a source region (260 n++, fig5, [96]).
Re claim 47, Islam modified above teaches the semiconductor device of Claim 45, wherein the drift region further comprises a third region (center part of n -type 220 under 530, fig5, [96]) beneath the central pillar (530 n+, fig5, [97]) and the outer pillars (540 P, fig5, [99]), the third region having the first conductivity type (n-type, [96]).
Claim(s) 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al. US 2022/0173227 in view of Lichtenwalner et al. US 2023/0087937 and Nishio et al. US 2013/0237042.
Re claim 39, Islam teaches the semiconductor device of Claim 28, wherein the substrate comprises silicon carbide (210, fig5, [74, 96]) having a hexagonal polytype and wherein the mesa stripe extends in the first direction (275 extends in Z, fig5, 13/14, [96]).
Islam does not explicitly show wherein the substrate having an off-cut angle towards a first direction relative to a crystallographic direction of the substrate along which implant channeling occurs.
Nishio teaches wherein the substrate comprises silicon carbide having a hexagonal polytype (10, fig1, [20]) and having an off-cut angle towards a first direction ([20]) relative to a crystallographic direction ((0001) plane, [20]) of the substrate along which implant channeling occurs.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Islam, Lichtenwalner and Nishio to have the off-cut of the SiC substrate with an off angle of 1-8 degrees. The motivation to do so is to achieve satisfactory epitaxial growth over the substrate (Nishio, [20]).
Re claim 40, Islam modified above teaches the semiconductor device of Claim 39, wherein the crystallographic direction comprises a <0001> crystallographic direction (Nishio, [20]).
Allowable Subject Matter
Claim 34-35, 37-38 and 44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to form a high voltage device with reduced on resistance and high power density.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812