DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US Pub. 2015/0146476).
Regarding claim 1, Fig. 3 of Zhang discloses a memory device comprising:
a first bit cell comprising a first inverter [combination of M1 and M2], the first inverter comprising a p-type transistor [M1] coupled to an n-type transistor [M2]; and
header circuitry [combination of M7 and M8] coupled to the first inverter and comprising a first header transistor [M8] and a second header transistor [M7] that are electrically connected in series, the first header transistor [M8] having a gate configured to receive a bias voltage [VDD], the second header transistor [M7] having a gate configured to receive a reference voltage [ground], a source coupled [coupled is electrically linking together, when M7 is on, is source is coupled to the drain of M8] to a drain of the first header transistor [M8], and a drain coupled to the first bit cell [110].
Regarding claim 2, Fig. 3 of Zhang discloses wherein the first header transistor and the second header transistor are p-type transistors [M8 and M7], and wherein a drain of the first header transistor [M8] is coupled to a source of the second header transistor [M7, coupled is equivalent to linking].
Regarding claim 3, Fig. 3 of Zhang discloses wherein the drain of the second header transistor [M7] is coupled to a source of the p-type transistor [M1] of the first inverter.
Regarding claim 4, Fig. 3 of Zhang discloses wherein the first bit cell further comprises a second inverter comprising a p-type transistor [M3] coupled to an n-type transistor [M4].
Regarding claim 5, Fig. 3 of Zhang discloses wherein the first inverter [M1 & M2] and the second inverter [M3 and M4] are cross-coupled by a storage node and an inverse storage node.
Regarding claim 6, Fig. 3 of Zhang discloses wherein the drain of the second header transistor [M7] is coupled to a source of the p-type transistor [M1] of the first inverter [combination of M1 and M2] and a source of the p-type transistor [M3] of the second inverter [combination of M3 and M4].
Regarding claim 7, Fig. 3 and Fig. 5 of Zhang discloses further comprising a second bit cell [one of a cell in array 510-0(m:0)] coupled to the header circuitry [Passive Write assist].
Regarding claim 8, Fig. 3 and Fig. 5 of Zhang discloses wherein the second bit cell [similar to Fig. 3] comprises a third inverter comprising a p-type transistor coupled to an n-type transistor [similar to M1 and M2 in Fig. 3], and a drain of the p-type transistor of the third inverter [similar to M1] coupled to the header circuitry [M7 and M8].
Regarding claim 9, Fig. 3 of Zhang discloses wherein the memory device is embedded in a field programmable gate array (FPGA).
Regarding claim 10, Fig. 5 of Zhang discloses wherein the first bit cell [top cell 510-n(m:0)]] and the second bit cell [510-0(m:0)]] share a common data node [BT] and inverse data node [BF].
Regarding claims 11 and 20, Fig. 3 and Fig. 5 of Zhang discloses a memory device comprising:
first header circuitry [combination M8 and M7] comprising a first header transistor [M8] and a second header transistor [M7] that are electrically connected in series, the first header transistor [M8] having a gate configured to receive a bias voltage [VDD], the second header transistor [M7] having a gate configured to receive a reference voltage [ground];
second header circuitry [another Passive write assist in Fig. 5, which is similar to the first header circuitry shows in Fig. 3] comprising a third header transistor [similar to M8 in Fig. 3] and a fourth header transistor [similar to M7 in Fig. 3] that are electrically connected in series, the third header transistor [M8] having a gate configured to receive the bias voltage [VDD, Fig. 3], the fourth header transistor having a gate configured to receive the reference voltage [ground];
a first bit cell [top SRAM bit cell 510-n(m:0)] and a second bit cell [bottom bit cell, 510_0(m:0)] coupled to drain of the second header transistor [M7] [one of Passive write assist, Fig. 5]; and a third bit cell [another bit cell in 510-n(m:0)] and a fourth bit cell [another cell in 510-0(m:0)] coupled to a drain of the fourth header transistor [another Passive write assist].
Regarding claim 12, Fig. 3 and Fig. 5 of Zhang discloses wherein the first header transistor [M8 and M7], the second header transistor [another Passive write assist similar to M8 and M7], the third header transistor [M8] , and the fourth header transistor [M7] are p- type transistors [they all are PMOS transistors].
Regarding claim 13, Fig. 3 of Zhang discloses wherein a drain of the first header transistor [M8] is coupled to a source of the second header transistor [M7], and a drain of the third header transistor [similar to M8] is coupled to a source of the fourth header transistor [similar to M7].
Regarding claim 14, Fig. 3 of Zhang discloses wherein: the first bit cell [top, Fig. 5] comprises: a first inverter comprising a p-type transistor [M1] coupled to an n-type transistor [M2]; and a second inverter comprising a p-type transistor [M3] coupled to an n-type transistor [M4]; the second bit cell [bottom cell, Fig. 5] comprises: a third inverter comprising a p-type transistor [similar to M] coupled to an n-type transistor [similar to M2]; and a fourth inverter comprising a p-type transistor [similar to M3] coupled to an n-type transistor [similar to M4]; the third bit cell [another top cell] comprises: a fifth inverter [similar to M1 and M2 in Fig. 3] comprising a p-type transistor [similar to M1] coupled to an n-type transistor [similar to M2]; and a sixth inverter comprising a p-type transistor [similar to M3] coupled to an n-type transistor [similar to M4]; and the fourth bit cell [another bottom cell] comprises: a seventh inverter [similar to Fig. 3] comprising a p-type transistor [similar to M1] coupled to an n-type transistor [similar to M2]; and an eighth inverter comprising a p-type transistor [similar to M3] coupled to an n-type transistor [similar to M4].
Regarding claim 15, Fig. 3 of Zhang discloses wherein: the drain of the second header transistor [M7] is coupled to a source of the p-type transistor [M1] of the first inverter, a source of the p-type transistor [M3] of the second inverter, a source of the p-type transistor of the third inverter [of bottom cell], and a source of the p-type transistor of the fourth inverter [of bottom cell]; and the drain of the fourth header transistor [M7] [another Passive write assist] is coupled to a source of the p-type transistor [anther top cell] of the fifth inverter, a source of the p-type transistor [second Pmos of top cell] of the sixth inverter, a source of the p- type transistor of the seventh inverter [PMOS of another bottom cell], and a source of the p-type transistor [other PMOS transistor of bottom cell] of the eighth inverter.
Regarding claim 16, Fig. 3 of Zhang discloses wherein: the first inverter [M1 and M2] and the second inverter [M3 and M4] are cross-coupled by a first storage node [Q1] and a first inverse storage node [Q2]; the third inverter and the fourth inverter are cross-coupled by a second storage node and a second inverse storage node [similar to Fig. 3]; the fifth inverter and the sixth inverter are cross-coupled by the second storage node and the second inverse storage node [similar to Fig. 3]; and the seventh inverter and the eighth inverter are cross-coupled by a third storage node and a third inverse storage node [similar to Fig. 3].
Regarding claim 17, Fig. 3 of Zhang discloses wherein the memory device is embedded in an field programmable gate array (FPGA).
Regarding claim 18, Fig. 5 of Zhang discloses wherein neighboring bit cells share a common data node [BT] and an inverse data node [BF].
Regarding claim 19, Fig. 3 of Zhang discloses memory device comprising:
a first bit cell comprising a first inverter [combination of M1 and M3] cross-coupled to a second inverter [combination of M3 and M4] by a first storage node [Q1] and a first inverse storage node [Q2]; and
a first header circuitry [combination of M8 and M7] comprising a first header transistor [M8] and a second header transistor [M7] that are electrically connected in series; the first header transistor [M8] having a gate configured to receive a bias voltage [VDD], the second header transistor [M7] having a gate configured to receive a reference voltage [ground], a source coupled to a drain of the first header transistor [M8], and a drain coupled to the first bit cell [110], the first header circuitry [M8 & M7] coupled to the first inverter and the second inverter [M1 and M3].
Response to Arguments
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive.
Applicant argues that Zhang does not teach or suggest the second header transistor having a source coupled to a drain of the first header transistor, and a drain coupled to the first bit cell. Applicant is reminded that the claims are examined in light of broadest reasonable interpretation. In addition, although the claims are examined in light of specification, limitations from specification are not read into the claimed. “Coupled” is broadly interpreted as electrical linking together. “Coupled” does not required directly connects. Therefore, when M7 is turned on, its source is coupled (electrically linking) to the drain of the first header transistor [M8] and its drain is coupled to the first bit cell [110].
Therefore, all applicant’s arguments were fully considered, they are not persuasive.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825