DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 04/23/2026 in which claims 1-3, 11, 13, 15, and 19 are amended has been entered of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baeck et al. (US Pub. 2018/0294018).
Regarding claim 1, Fig. 2 of Baeck discloses a memory device comprising:
a first bit cell [11_1] couple to a node [nVDA1] comprising a first inverter [I1], the first inverter comprising a p-type transistor [within I1] coupled to an n-type transistor [within I2]; and
header circuitry [14_1] coupled to the first inverter [N1] and comprising a first header transistor [P3] comprising a first gate configured to receive a bias voltage [PD], a first source configured to receive a first voltage source [VDDA], and a first drain; and a second header transistor [P4] comprising a second gate configured to receive a reference voltage [voltage output at a node between P1 and P2], a second source couple to the first drain of the first header transistor [P3], and a second drain directly connected to the node [nVDA1], and the second header transistor [P4] is electrically connected in series with the first header transistor [P3].
Regarding claim 2, Fig. 2 of Baeck discloses wherein the first header transistor [P3] and the second header transistor [P4] are p-type transistors [paragraph 0037].
Regarding claim 3, Fig. 2 of Baeck discloses wherein the second drain of the second header transistor [P4] is coupled to a source of the p-type transistor of the first inverter [within I1].
Regarding claim 4, Fig. 2 of Baeck discloses wherein the first bit cell further comprises a second inverter [I2] comprising a p-type transistor [inherent for SRAM] coupled to an n-type transistor [within I2].
Regarding claim 5, Fig. 2 of Baeck discloses wherein the first inverter [I1] and the second inverter [I2] are cross-coupled by a storage node and an inverse storage node.
Regarding claim 6, Fig. 2 of Baeck discloses wherein the drain of the second header transistor [P4] is coupled to a source of the p-type transistor [within I1] of the first inverter [I1] and a source of the p-type transistor [within I2] of the second inverter [I2].
Regarding claim 7, Fig. 2 of Baeck discloses further comprising a second bit cell [11_2] coupled to the header circuitry [14_1].
Regarding claim 8, Fig. 2 of Baeck discloses wherein the second bit cell [similar 11_1] comprises a third inverter [similar to I1] comprising a p-type transistor coupled to an n-type transistor [similar to I1], and a drain of the p-type transistor of the third inverter [similar to I1] coupled to the header circuitry [14_1].
Regarding claim 9, Fig. 2 of Baeck discloses wherein the memory device is embedded in a field programmable gate array (FPGA).
Regarding claim 10, Fig. 2 of Baeck discloses wherein the first bit cell [11_1] and the second bit cell [11_2] share a common data node [DATA_t in 13] and inverse data node [DATA_c in 13].
Regarding claims 11 and 20, Fig. 3 and Fig. 5 of Zhang discloses a memory device comprising:
first header circuitry [14_1] comprising a first header transistor [P3] comprising a first gate configured to receive a bias voltage [PD], a first source configured to receive a first voltage source [VDDA], and a first drain,
a second header transistor [P4] comprising a second gate configured to receive a reference voltage [a voltage at anode between P1 and P2], a second source coupled to the first drain of the first header transistor [P3], and a second drain directly connected to a first node [nVDA1], wherein the second header transistor [P4] is connected between the first transistor [P3] and the first node [nVDA1], and the second header transistor [P4] is electrically connected in series with the first header transistor [P3];
and a second header transistor [M7] that are electrically connected in series, the first header transistor [M8] having a gate configured to receive a bias voltage [VDD], the second header transistor [M7] having a gate configured to receive a reference voltage [ground];
second header circuitry [14_2] comprising a third header transistor [similar to P3] and a fourth header transistor [similar to P4] that are electrically connected in series [similar to P3 and P4 connection], the third header transistor [similar to P3] having a third gate configured to receive the bias voltage [similar to PD], the fourth header transistor [similar to P4] having a third gate configured to receive the reference voltage [similar to the voltage received by P4];
a first bit cell [1110_1, Fig. 16] and a second bit cell [1110_2, Fig. 16] coupled to the first node [at node VDA1, Fig. 16]; and a third bit cell [1110_3, Fig. 16)] and a fourth bit cell [1110_4, Fig. 16] coupled to a second node [VDAn] coupled to a fourth drain of the fourth header transistor.
Regarding claim 12, Fig. 2 of Baeck discloses wherein the first header transistor [P3], the second header transistor [P4], the third header transistor [similar to P3] , and the fourth header transistor [similar to P4] are p- type transistors [they all are PMOS transistors, paragraph 0037].
Regarding claim 13, Fig. 2 of Baeck discloses wherein a third drain of the third transistor [similar to P3] is coupled to a fourth source of the fourth header transistor [similar to P4].
Regarding claim 14, Fig. 16 of Baeck discloses wherein: the first bit cell [1110_1] comprises: a first inverter [similar to I1 in Fig. 2] comprising a p-type transistor [similar to I1 in Fig. 2] coupled to an n-type transistor [within I1]; and a second inverter comprising a p-type transistor [similar to I2] coupled to an n-type transistor; the second bit cell [1110_2] comprises: a third inverter comprising a p-type transistor [similar to I1] coupled to an n-type transistor; and a fourth inverter [similar to I2] comprising a p-type transistor coupled to an n-type transistor ; the third bit cell [1110_3] comprises: a fifth inverter [similar to I1] comprising a p-type transistor coupled to an n-type transistor; and a sixth inverter [similar to I2] comprising a p-type transistor coupled to an n-type transistor; and the fourth bit cell [1110_4] comprises: a seventh inverter [similar to I1] comprising a p-type transistor coupled to an n-type transistor; and an eighth inverter [similar to I2] comprising a p-type transistor coupled to an n-type transistor.
Regarding claim 15, Fig. 2 of Baeck discloses wherein: the first node nVDA1 is coupled to a source of the p-type transistor of the first inverter [I1], a source of the p-type transistor of the second inverter [I2], a source of the p-type transistor of the third inverter [of cell 1110_2], and a source of the p-type transistor of the fourth inverter [similar to I2 of second cell]; and the drain of the fourth header transistor [similar to P4] is coupled to a second node [VDA2], and the second node is coupled to a source of the p-type transistor [similar to I1, belong to 1110_3 in Fig. 16], a source of the p-type transistor [within the inverter] of the sixth inverter [similar o I2], a source of the p- type transistor of the seventh inverter [PMOS of another bottom cell], and a source of the p-type transistor [other PMOS transistor of bottom cell] of the eighth inverter.
Regarding claim 16, Fig. 2 of Baeck discloses wherein: the first inverter [I1] and the second inverter [I2] are cross-coupled by a first storage node [a] and a first inverse storage node [b]; the third inverter [similar to I1] and the fourth inverter [similar to I2] are cross-coupled by a second storage node and a second inverse storage node [similar 11_1]; the fifth inverter [belong to cell 1110_3 in Fig. 16] and the sixth inverter [similar to I2] are cross-coupled by the second storage node and the second inverse storage node; and the seventh inverter and the eighth inverter are cross-coupled by a third storage node and a third inverse storage node [similar to 11_1].
Regarding claim 17, Fig. 2 of Baeck discloses wherein the memory device is embedded in an field programmable gate array (FPGA).
Regarding claim 18, Fig. 5 of Zhang discloses wherein neighboring bit cells share a common data node [DATA_t, within 13] and an inverse data node [DATA_c in 13].
Regarding claim 19, Fig. 2 od Baeck discloses memory device comprising:
a first bit cell [11_1] coupled to a node [nVDA1] and comprising a first inverter [I1] cross-coupled to a second inverter [I2] by a first storage node [a] and a first inverse storage node [b]; and
a first header circuitry [14_1] comprising a first header transistor [P3] comprising a first gate configured to receive a bias voltage [PD], a first source configured to receive a first voltage source [VDDA], and a first drain: and
a second header transistor [P4] comprising a second gate configured to receive a reference voltage [voltage between P1 and P2], a second source coupled to the first drain of the first header transistor [P3], and a second drain coupled to the node [nVDA1], wherein the first header circuit [14_1] directly connected to the first inverter [I1] and the second inverter [I2], and wherein the second header transistor [P4] is connected between the first header transistor [P3] and the node [nVDA1], and the second header transistor [P4] is connected in series with the first header transistor [P3].
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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