Prosecution Insights
Last updated: July 17, 2026
Application No. 18/213,765

ELECTRON-OPTICAL DEVICE

Non-Final OA §102§103
Filed
Jun 23, 2023
Priority
Dec 23, 2020 — EU 20216933.0 +2 more
Examiner
CHOI, JAMES J
Art Unit
2878
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ASML Holding N.V.
OA Round
3 (Non-Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
262 granted / 389 resolved
-0.6% vs TC avg
Strong +47% interview lift
Without
With
+46.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
32 currently pending
Career history
439
Total Applications
across all art units

Statute-Specific Performance

§103
98.2%
+58.2% vs TC avg
§102
1.0%
-39.0% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 389 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments filed on 11/12/25 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. The amendment necessitates the new ground(s) of rejection presented due to the added language in the independent claims. It is noted that the claims recite “a first region corresponding to the array of apertures” which is broad enough to read on the first region of the array substrate comprising a subset of the apertures in the array substrate. Status of the Application Claim(s) 1-16, 18-20 is/are pending. Claim(s) 1-16, 18-20 is/are rejected. Claim Rejections – 35 U.S.C. § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: PNG media_image1.png 158 934 media_image1.png Greyscale Claim(s) 1-3, 8, 11, 15-16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by (or under 35 U.S.C. § 103 as being unpatentable over) Yagi et al. (US 20020005491 A1) [hereinafter Yagi]. PNG media_image2.png 703 1050 media_image2.png Greyscale [AltContent: textbox (annotated)][AltContent: textbox (Array substrate)][AltContent: textbox (Adjoining substrate)][AltContent: textbox (First region)][AltContent: textbox (Another region)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: textbox (Spacer)][AltContent: connector][AltContent: rect] Regarding claim 1, Yagi teaches a lens assembly for manipulating electron beamlets (see figs 1, 6, 7, 11), comprising an electron-optical device for manipulating electron beamlets, the device comprising: an array substrate (see e.g. fig 1: 3, fig 6: 52, fig 7: 63) in which an array of apertures is defined for the path of electron beamlets (see e.g. 53), the array substrate having a thickness which is stepped so that the array substrate is thinner in a first region corresponding to the array of apertures (e.g. region around one 53, alternately see fig 4, with multiple apertures per unsupported region) than another region of the array substrate (see figs 1,6,7, outer part); an adjoining substrate (e.g. 2, 51, 62) in which another array of apertures is defined for the path of the electron beamlets (see figs 1,6,7); and a spacer (e.g. 59 or 69; alternately see fig 4: 34) disposed between the substrates to separate the substrates such that the opposing surfaces of the substrates are parallel to each other (see figs 1, 6), the spacer having an inner surface that defines an opening for the path of the electron beamlets (see same, [0045]), wherein the inner surface faces the path of the beamlets (see same), the spacer is in contact with the another region of the array substrate (see figs 1, 6, 7), wherein the electron-optical device is configured to provide a potential difference between the substrates (see e.g. [0008,43]). Yagi may fail to explicitly disclose the first region of the array substrate is unsupported. However, in a different embodiment, Yagi teaches that the inner spacer can be formed in a wide variety of shapes and materials, including wherein a first region of the array substrate is unsupported (see e.g. Yagi, [0044], fig 4; see also figs 6,7, noting unsupported regions closest to each aperture hole). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to select the use of different shapes and materials, including the known effective configurations having unsupported apertures, in the manner taught by Yagi. It is noted that simple substitution of one known element for another to obtain predictable results supported a prima facie obviousness. See MPEP 2143. Regarding claim 2, Yagi teaches one of the array substrate and the adjoining substrate is upbeam of the other (see Yagi, e.g. figs. 1,6). Regarding claim 3, Yagi may fail to explicitly disclose the upbeam substrate has a higher potential difference relative to a reference potential than the downbeam substrate. However, setting an arbitrary reference potential would have been obvious as a routine skill in the art, for example to simplify calculations by setting it as the downbeam potential. Alternately, the reference potential can be constructively defined as any number closer to the downbeam substrate potential than the upstream. Regarding claim 8, Yagi teaches the array substrate comprises a first wafer etched to generate the regions having different thicknesses (see e.g. Yagi, fig 9e, [0049]; note wafer shape). Regarding claim 11, Yagi teaches the array of apertures defined in the adjoining substrate has the same pattern as the array of apertures defined in the array substrate (see Yagi, figs, 1,6,7; required for operation of system). Regarding claim 15, Yagi teaches a detector array configured to detect electrons emitted from the sample Regarding claim 16, Yagi teaches an objective lens assembly for manipulating electron beamlets, the objective lens assembly comprising an electron-optical device for manipulating electron beamlets, the device comprising: an array substrate (see e.g. fig 1: 3, fig 6: 52, fig 7: 63) in which an array of apertures is defined for the path of electron beamlets (see e.g. 53), the array substrate having a thickness which is stepped so that the array substrate is thinner in a first region corresponding to the array of apertures than another region of the array substrate (see figs 1,6,7); an adjoining substrate (e.g. 2, 51, 62) in which another array of apertures is defined for the path of the electron beamlets (see figs 1,6,7); a spacer (e.g. 59 or 69; alternately see fig 4: 34) disposed between the substrates to separate the substrates such that the opposing surfaces of the substrates are parallel to each other (see figs 1, 6), the spacer having an inner surface that defines an opening for the path of the electron beamlets (see same, [0045]), wherein the inner surface faces the path of the beamlets (see same), the spacer is in contact with the another region of the array substrate (see figs 1, 6, 7), a detector assembly (see fig. 11: 512), wherein the electron-optical device is configured to provide a potential difference between the substrates (see e.g. [0008,43]). Yagi may fail to explicitly disclose the first region of the array substrate is unsupported. However, in a different embodiment, Yagi teaches that the inner spacer can be formed in a wide variety of shapes and materials, including wherein a first region of the array substrate is unsupported (see e.g. Yagi, [0044], fig 4; see also figs 6,7, noting unsupported regions closest to each aperture hole). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to select the use of different shapes and materials, including the known effective configurations having unsupported apertures, in the manner taught by Yagi. It is noted that simple substitution of one known element for another to obtain predictable results supported a prima facie obviousness. See MPEP 2143. Regarding claim 18, Yagi teaches the detector assembly is down beam of the electron-optical device (see Yagi, fig 11). Regarding claim 19, Yagi teaches the detector assembly comprising a detector array (see Yagi, [0054]; alternately note well known use of segmented detector arrays in the art) configured to detect electrons emited from the sample (see [0054]). Regarding claim 20, Yagi teaches a lens assembly for manipulating electron beamlets, the objective lens assembly comprising an electron-optical device for manipulating electron beamlets, the device comprising: an array substrate (see e.g. fig 1: 3, fig 6: 52, fig 7: 63) in which an array of apertures is defined for the path of electron beamlets (see e.g. 53), the array substrate having a thickness which is stepped so that the array substrate is thinner in a first region corresponding to the array of apertures than another region of the array substrate (see figs 1,6,7); an adjoining substrate (e.g. 2, 51, 62) in which another array of apertures is defined for the path of the electron beamlets (see figs 1,6,7); a spacer (e.g. 59 or 69; alternately see fig 4: 34) disposed between the substrates to separate the substrates such that the opposing surfaces of the substrates are parallel to each other (see figs 1, 6), the spacer having an inner surface that defines an opening for the path of the electron beamlets (see same, [0045]), wherein the inner surface faces the path of the beamlets (see same), the spacer is in contact with the another region of the array substrate (see figs 1, 6, 7), a detector assembly (see fig. 11: 512), wherein the electron-optical device is configured to provide a potential difference between the substrates (see e.g. [0008,43]), the lens assembly is a condenser lens array and is configured to generate the electron beamlets from an electron beam emitted by a source (see e.g. [0054], 502-503). Yagi may fail to explicitly disclose the first region of the array substrate is unsupported. However, in a different embodiment, Yagi teaches that the inner spacer can be formed in a wide variety of shapes and materials, including wherein a first region of the array substrate is unsupported (see e.g. Yagi, [0044], fig 4; see also figs 6,7, noting unsupported regions closest to each aperture hole). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to select the use of different shapes and materials, including the known effective configurations having unsupported apertures, in the manner taught by Yagi. It is noted that simple substitution of one known element for another to obtain predictable results supported a prima facie obviousness. See MPEP 2143. Claim(s) 4 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi, as applied to claim 1 above, and further in view of Ono et al. (US 20040061064 A1) [hereinafter Ono]. Regarding claim 4, Yagi may fail to explicitly disclose a surface of the array substrate between the first region of the array substrate and the another region of the array substrate is orthogonal to the surface of the array substrate facing the adjoining substrate. However, it would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to adjust the internal shapes of the plates as a routine skill in the art, for example to interface with different lens holder shapes. Yagi teaches the system being formed with etching and milling, which were well known in the art to provide the ability to form angled or orthogonal side walls and other features of electrodes. Additionally, the use of electrode plates having orthogonal internal surfaces was well known in the art at the time the application was effectively filed. For example, Ono teaches a known effective aperture plate assembly comprising a surface of the substrate between the thinner region of the substrate and the other region of the substrate is orthogonal to the surface of the substrate facing the adjoining substrate (see Ono, fig 2a), which may be formed with low cost manufacturing (see [0148]). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to provide a substrate having at least one orthogonal surface as claimed, as a routine skill in the art based on available equipment and manufacturing expertise. Claim(s) 5, 9 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi, as applied to claim 1 above, and further in view of Steenbrink et al. (US 20110216299 A1) [hereinafter Steenbrink]. Regarding claim 5, Yagi may fail to explicitly disclose the inner surface is shaped such that a creep path between the substrates over the inner surface is longer than a minimum distance between the substrates. However, Steenbrink teaches a spacer structure that mitigates problems associated with flashovers, reducing problems with electrostatic discharge where it is not wanted (see Steenbrink, [0084-86], fig 5) wherein a creep path between the substrates over the inner surface is longer than a minimum distance between the substrates (see fig 5). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to combine the teachings of Steenbrink in the system of the prior art, because a skilled artisan would have been motivated to look for ways to improve control over the system, including better controlling flashovers and electrostatic discharge, as taught by Steenbrink. Regarding claim 9, the combined teaching of Yagi may fail to explicitly disclose the claimed limitation(s). However, the differences would have been obvious in view of Steenbrink, for similar reasons as claim 5 above. Therefore, the combined teaching of Yagi and Steenbrink teaches the inner surface is stepped with an upper beam portion distanced further away from the path of the beamlets than a lower beam portion (thicker on negative electrode, see Steenbrink, [0083], which corresponds to the outer electrodes of an electrostatic lens, as well known in the art). Claim(s) 6 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi and Steenbrink, as applied to claim 5 above, and further in view of Hatekeyama et al. (US 20160307726 A1) [hereinafter Hatekayama]. Regarding claim 6, the combined teaching of Yagi and Steenbrink may fail to explicitly disclose the inner surface comprises corrugations, preferably the corrugations are concentric and/or the corrugations surround the opening. However, under the broadest reasonable interpretation of the claims, the interior surface comprises a corrugation. It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to form the spacer out of multiple pieces (e.g. halves, quadrants), for example to enable cheaper or simpler manufacturing, thereby providing multiple corrugations. Alternately, it was well known in the art to use corrugated surfaces for insulators. For example, Hatakeyama teaches a system to increase creeping dielectric strength by using corrugated surfaces (see fig 209) which can further suppress discharge (see [1320-1321]). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to combine the teachings of Hatakeyama in the system of the combined prior art, thereby providing corrugated surfaces, as a routine skill in the art to enable even higher creeping discharge strength and potentially suppress discharge where it is needed. Claim(s) 7 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi, as applied to claim 1 above, and further in view of Matsumoto (US 20160141142 A1). Regarding claim 7, Yagi teaches a first wafer (see Yagi, fig 1,6,7) in which the aperture array is defined, disposed in contact with the spacer (see figs 1,6,7). Yagi may fail to explicitly disclose a second wafer disposed on a surface of the first wafer in a region not corresponding to the aperture array. However, the use of auxiliary wafers was well known in the art at the time the application was effectively filed. For example, Matsumoto teaches mounting an aperture lens array on a second wafer (see e.g. Matsumoto, fig 3: 212) disposed on a surface of the first wafer in a region not corresponding to the aperture array (see fig 3), which enables e.g. an interfacing system (see fig 4). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to combine the teachings of Matsumoto in the system of the prior art in order to enable the intended operation of providing an interface for the electrodes, while also enabling further flexibility to mount the system wherever it is needed, using known effective wafer mounting, in the manner taught by Matsumoto. Claim(s) 10 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi, as applied to claim 1 above, and further in view of Gerthsen et al. (US 20100065741 A1) [hereinafter Gerthsen]. Regarding claim 10, Yagi may teaches a coating is provided on the surface of at least one of the substrates (see Yagi, e.g. gold, [0048]; see also electrodes). It is unclear if the coating is 0.5 Ohms/square or lower. However, the use of different protective coating thicknesses was well known in the art. For example, Gerthsen teaches a range of gold coatings thicknesses are usable for an electron lens shielding layer, including a thickness of 5 μm (exceeds 0.5 Ω/sq for gold resistivity at 2.2 μΩ-cm). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to try to combine the teachings of Gerthsen in the system of the prior art, to provide additional shielding while still enabling known effective operation of the lens, in the manner taught by Gerthsen. Claim(s) 12-13 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi, as applied to claim 1 above, and further in view of Fichter et al. (US 20160314931 A1) [hereinafter Fichter]. Regarding claim 12, Yagi may fail to explicitly disclose a protective resistor configured to provide controlled discharge of stored electric charges in the lens to prevent damages. However, the use of resistors as part of power protection circuits was well known in art at the time the application was effectively filed. For example, Fichter teaches a known effective system to provide control over even voltages in charged particle beams (see Fichter, abstract, [0034]) which enables the ability to provide a measurement and control loop (e.g. [0027]) and provide even multiple high voltages (see abstract), comprising a protective resistor (see e.g. feedback resistor, [0021]; fig 8, etc) configured to provide controlled discharge of stored electric charges in the lens to prevent damages (natural result of using resistor for feedback control, which would naturally prevent damages to downstream components due to non-corrected voltages and noise). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to combine the teachings of Fichter in the system of the prior art because a skilled artisan would have been motivated to look for ways to enable the intended operation of providing more effective control over the voltages. Regarding claim 13, the combined teaching of Yagi and Fichter teaches a circuit board (see e.g. Fichter, [0031]) electrically connected to the array substrate and/or the adjoining substrate; wherein the protective resistor is electrically connected to the circuit board (on the PCB, see [0031]). Claim(s) 14 is/are rejected under 35 U.S.C. § 103 as being unpatentable over Yagi and Fichter, as applied to claim 13 above, and further in view of Burgin et al. (US 5920076 A) [hereinafter Burgin] as evidenced by Zhang (US 20120080148 A1). Regarding claim 14, the combined teaching of Yagi and Fichter teaches a connector (required for intended operation of system) configured to electrically connect the array substrate or the adjoining substrate to the circuit board (required for intended operation of connecting components to PCBs). The combined teaching may fail to explicitly disclose wherein the connector is surrounded by material of 25 kV/mm or greater. However, it is noted it would have been obvious as a routine skill in the art to place the device in a room or basement where it is surrounded by building materials of greater than 25kV/mm. Nevertheless it is noted that it was well known in the art to use jacketing material having greater than 25 kV/mm. For example, Burgin teaches PTFE (possessing 55kV/mm dielectric strength, see Zhang, [0009]) is a known effective insulating structure (see Burgin, col 13, lines 58-60) and teaches a flexible system to enable the ability to provide effective routing and sealing while ensuring effective electrical and mechanical connection (see e.g. fig 9). It would have been obvious to a person having ordinary skill in the art at the time the application was effectively filed to combine the teachings of Burgin in the system of the prior art because a skilled artisan would have been motivated to look for ways to enable the intended operation of the system, including using the known effective PTFE insulator, as taught by Burgin. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to James Choi whose telephone number is (571) 272 – 2689. The examiner can normally be reached on 8:00 am – 5:30 pm M-T, and every other Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Robert Kim can be reached on (571) 272 – 2293. The fax phone number for the organization where this application or proceeding is assigned is (571) 273 – 8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAMES CHOI/Examiner, Art Unit 2881
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Prosecution Timeline

Jun 23, 2023
Application Filed
Aug 12, 2025
Non-Final Rejection mailed — §102, §103
Nov 12, 2025
Response Filed
Jan 06, 2026
Final Rejection mailed — §102, §103
Mar 05, 2026
Response after Non-Final Action
Mar 31, 2026
Request for Continued Examination
Apr 07, 2026
Response after Non-Final Action
Jul 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+46.6%)
2y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 389 resolved cases by this examiner. Grant probability derived from career allowance rate.

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