Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on 29 December 2025 is acknowledged. Claims 10-17 stand as canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210305119 (Mallik et al) and US 20180076110 (Agarwal et al).
As to claim 1: Mallik teaches a chip packaging structure having a heat dissipation plate, comprising:
a substrate, having a first surface and a second surface opposite to each other (Fig 15A, 220);
at least one chip, disposed on the first surface of the substrate and electrically connected to the substrate (205 on top of 220); and
the heat dissipation plate, wherein the heat dissipation plate is bonded to the first surface of the substrate (275 bonded by 1460), the heat dissipation plate and the substrate form a cavity in a surrounding manner for holding the chip therein (275 and 1460 form cavity), the heat dissipation plate and the chip are connected by at least one fixed connector (comprising 230+250+273), a material is filled in a region among the heat dissipation plate, the chip and the fixed connector (455), and a connection strength between the fixed connector and the chip or the heat dissipation plate is greater than a connection strength between the material and the chip or the heat dissipation plate (273 formed integrally with heat dissipation plate, i.e. will have a greater connection to the heat dissipation plate than with surrounding material 455. See Fig 9A and ¶0103).
Mallik fails to explicitly teach the material being a thermal interface material, rather teaching it may be an underfill material (¶0061).
Agarwal teaches a structure similar to that of Mallik, wherein fixed connectors between a chip and a heat dissipation plate are filled among the heat dissipation plate, the chip, and the fixed connector (Fig 1H, 119 ¶0037).
The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art.
As to claim 2: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 1. Mallik further teaches wherein the heat dissipation plate and the chip are connected by a plurality of fixed connectors (plural 230+250+273), and the fixed connectors are at least distributed at an edge of a non-functional surface of the chip (connectors at edge of top-side of 205).
As to claim 3: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 2. Mallik further teaches wherein the fixed connectors at least comprise first fixed connectors and second fixed connectors (first connectors those with 1460 in Fig 14B, second connectors those with 250 in Fig 14B), a connection strength between the first fixed connectors and the chip or the heat dissipation plate (connection of pad 273 of first connector integral with heat dissipation plate) is greater than a connection strength between the second fixed connectors and the chip or the heat dissipation plate (250 of second connector not integral with the chip. i.e., has a lower connection strength than that of the first connector), the first fixed connectors are distributed at four corners and/or four sides of the non-functional surface of the chip (second connectors shown at edge along line B-B’ and disclosed to form EMI shield around die ¶0117), and the second fixed connectors are distributed in a region between the first fixed connectors on two opposite sides (second connectors between first connectors).
As to claim 4: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 3. Malik further teaches wherein an area of a fixed connection region between the first fixed connectors and the chip or the heat dissipation plate is larger than an area of a fixed connection region between the second fixed connectors and the chip or the heat dissipation plate (pad portion of first connectors shown as larger than those of second connector).
As to claim 5: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 1. Mallik further teaches wherein the fixed connector is a bonded metal block disposed between the chip and the heat dissipation plate (connector comprising 230+250+273 bonded and made of metal).
As to claim 6: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 5. Mallik further teaches wherein the chip has a functional surface towards the first surface of the substrate and a non-functional surface opposite to the functional surface (bottom and top surfaces of 205, respectively), and at least one chip-side metal block is disposed on the non-functional surface of the chip (metal block on top surface of 205).
As to claim 7: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 6. Mallik further teaches wherein the heat dissipation plate comprises a top cover plate and a side cover plate extending downward along an edge of the top cover plate (top cover 271, side cover plates being pad portions on far ends of plate in Fig 15A), the top cover plate is bonded above the non-functional surface of the chip (271 above top of 205), a tail end of the side cover plate is connected to the first surface of the substrate (connected via bumps 1460), at least one cover plate-side metal block is disposed on an inner surface of the top cover plate (plural 230+250+273 with portion 273 disposed on inside surface of 271), a position and a number of the at least one cover plate-side metal block are set corresponding to those of the at least one chip-side metal block (numbers of 273/230 correspond), and the cover plate-side metal block and the chip-side metal block are bonded to form the bonded metal block (bonded with intermediate 250).
As to claim 8: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 1. Mallik further teaches wherein the heat dissipation plate is a metal heat dissipation plate (271 may be metal ¶0063).
As to claim 9: Mallik + Agarwal teaches the chip packaging structure having a heat dissipation plate according to claim 1. Mallik further teaches wherein a solder ball is disposed on the functional surface of the chip (unlabeled solder balls on underside of 205), the functional surface of the chip is electrically connected to a bonding pad on the first surface of the substrate through the solder ball (¶0054), and an underfill is filled between the chip and the substrate (1455).
Conclusion
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/Corbyn D Mellinger/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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