Attorney’s Docket Number: 230371-US-ORG1
Filing Date: 6/26/2023
Inventors: Jain et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 7/29/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 7/29/2026 in reply to the restriction in paper no. 6, mailed on 3/31/2026, has been entered. The present Office action is being made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-9 and 11-20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 12-14 are rejected under 35 U.S.C. 112(d) as being of improper dependent form.
The claims are improper for failing to further limit the subject matter of the claim upon which they depend, or for failing to include all the limitations of the claim upon which they depend. Claims 12-14 are incomplete because claim 10, on which they depend from, has been cancelled. Applicant may cancel the claims, amend the claims to place the clams in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims comply with the statutory requirements.
See MPEP § 608.01(n)V where it is stated that if the base claim has been cancelled, a claim that is directly or indirectly dependent thereon should be rejected as incomplete.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aleksov (US 2019/0198447).
Regarding claim 20, Aleksov (see, e.g., fig. 1) shows all aspects of the instant invention including an integrated circuit (IC) device comprising a chip-on-wafer device (CoW) comprising:
An interposer substrate 106 comprising:
A plurality of metal layers 114/116
A plurality of hybrid bonding connectors 114/116 exposed through a surface of the interposer, and
Electrical connections 114/116 between the connectors of the interposer and the metal layers, and
A plurality of field-programmable gate array (FPGA) chiplets 102/104 disposed faced down on the surface of the interposer
wherein:
The hybrid connectors 114/116 comprise metal pillars perpendicular to the surface of the interposer (see, e.g., fig. 10)
A spacing between adjacent pillars is 10 µm or less (see, e.g., ¶0030)
The chiplets comprise respective connectors 108/110 exposed through surfaces of the chiplets in alignment with the connectors 114/116 of the interposer
The metal layers 114/116 are patterned to provide inter-die connections amongst the chiplets
The metal layers 114/116 are patterned to provide intra-die connections for one or more of the chiplets
The chiplets 102/104 are configured to communicate with one another via the inter-die connectors 110 of the chiplets
Regarding claim 15, Aleksov (see, e.g., fig. 1) shows all aspects of the instant invention including a device comprising a CoW comprising:
An interposer substrate 106 comprising:
A plurality of metal layers 114/116
A plurality of connectors 114/116 exposed through a surface of the interposer, and
Connections 114/116 between the connectors of the interposer and the metal layer, and
Multiple IC dies 102/104 of a FPGA on the surface of the substrate
wherein:
The connectors 114/116 comprise metal pillars perpendicular to the surface of the interposer (see, e.g., fig. 10)
A spacing between adjacent pillars is not greater than 10 µm (see, e.g., ¶0030)
The dies comprise respective connectors 108/110 exposed through surfaces of the dies in alignment with the connectors of the interposer
The metal layers 114/116 are patterned to provide inter-die connections amongst the dies
The metal layers 114/116 are patterned to provide intra-die connections amongst the dies
Regarding claim 1, Aleksov (see, e.g., fig. 1) shows all aspects of the instant invention including a device comprising a CoW comprising:
An interposer substrate 106 comprising:
A plurality of metal layers 114/116
A plurality of connectors 114/116 exposed through a surface of the interposer, and
Connections 114/116 between the connectors of the interposer and the metal layer, and
A FPGA distributed amongst multiple IC dies 102/104 disposed faced down on the surface of the substrate
wherein:
The connectors 114//116 comprise metal pillars perpendicular to the surface of the interposer (see, e.g., fig. 10)
The spacing between adjacent pillars is not greater than 10 µm (see, e.g., ¶0030)
The dies 102/104 comprise respective connectors 108/110 exposed through surfaces of the dies in alignment with the connectors 114/116 of the interposer 106
The metal layers 114/116 are patterned to provide inter-die connections amongst the dies
The metal layers 114/116 are patterned to provide intra-die connections for the dies
The dies 102/104 are configured to communicate with one another via the inter-die connections
Regarding claims 20, 15, and 1, Aleksov further teaches that the dies/chiplets 102/104 may comprise FPGAs (¶0027), and that the interposer connectors 114/116 provide conductive coupling between connectors 108/110 of adjacent dies/chiplets (¶0028,00300). Thus, where the dies comprise elements of an FPGA distributed across multiple dies, the disclosed connectors provide the capability for the FPGA dies to communicate with each other.
With respect to the recitation that the FPGA chiplets/dies are configured to communicate with one another via the inter-die connections using a non-serialized protocol native to FPGA, this limitation is a functional limitation of the FPGA chiplets/dies and their interconnections. Under MPEP§2114, a functional limitation is generally satisfied by a prior art structure that is capable of performing the recited function. The disclosed FPGA chiplets/dies 102/104 and connectors 114/116 are capable of providing direct communication between the dies without requiring serialization/deserialization circuitry. Accordingly, the claimed communication functionality does not distinguish the claimed device from the structure disclosed by Aleksov.
Regarding claim 16-19, Aleksov (see, e.g., ¶0027/ll.4-5 and fig. 1) shows the device wherein:
The connectors of the dies comprise connectors along edges 110 and within a central region 108 of the surface of the die
The dies 102/104 are configured to communicate with one another via the connectors 110 along the edges of the dies
The dies 102/104 are each configured to use the intra-die connections within the central region for intra-die communications
Aleksov, however, fails to show that the parameters provided to the dies are power, clock and configuration parameters. These limitations, however, are a description of the functions of the dies. Under MPEP§2114, a structural limitation expressed functionally is satisfied by a prior art structure that is capable of performing the recited function.
Aleksov (see, e.g., fig. 1) explicitly shows dies 102/104 formed on an interposer 106. The interposer 106, by virtue of its inherent architecture, carries with it the capability to route clock, power and configuration signals to the dies 102/104 through its metal layers, electrical connections and hybrid connectors 114/116 (see, e.g., ¶0028). The interposer of Aleksov, which already routes signals through the central connectors of the dies, is, therefore, structurally capable of routing power, clock, and configuration signals through those same connectors. Routing signals is an intrinsic property of the interposer of Aleksov. Therefore, the interposer of Aleksov is inherently capable of providing clock, power and configuration signals through the central connectors of the dies.
Regarding claim 7, Aleksov (see, e.g., fig. 1) shows the device wherein:
The connectors of the dies comprise connectors 108 within central regions of the dies 102/104, and
The dies are configured to use the intra-die connections and the connectors within the central region of the dies for intra-die communications
Regarding claim 8, see the comments above in paragraphs 14-17 with respect to claims 7 and 18 which are considered repeated here.
Regarding claim 2, Aleksov (see, e.g., fig. 12) shows the device further comprising a super interposer substrate 902 and multiple instances 1202 of the CoW on the super interposer.
Regarding claim 3, Aleksov (see, e.g., fig. 1) shows the device wherein:
The connectors of the dies comprise connectors along one or more edges 110 of the surfaces of the dies
The dies communicate with each other via the edge connectors 110 of the dies and the metal layers 116 and the connections of the interposer
See also the comments above in paragraphs 12-13 with respect to claims 20, 15 and 1 which are considered repeated here.
Regarding claim 6, Aleksov shows the dies communicate with one another via the edge connectors 110 of the dies and the connections, and metal layers 116 of the interposer.
Synchronously in digital circuit design means that data transfer is governed by a common clock signal. Aleksov (see, e.g., ¶0027) teaches that the dies are FPGA, which are inherently synchronous. The limitation “communicate synchronously” is then considered functional language that describes an inherent property of the FPGA dies of Aleksov.
See also the comments above in paragraphs 12-13 with respect to claim 20, 15 and 1 which are considered repeated here.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov in view Saban.
Regarding claim 11, Aleksov (see, e.g., fig. 1) shows the connectors of the interposer 116 and the dies 110, and the metal layers 116 of the interposer provide inter-die connections. He, however, fails to teach that they provide more than 3000 connections per mm. Saban, in a similar device to Aleksov, teaches that providing a large number of connections enables high-bandwidth connectivity between the dies by integrating massive quantities of resources within a single package. However, although Saban teaches providing more than 10,000 die-to-die connections, he fails to specify more than 3000 connections per mm. See, e.g., Saban: p.4/ll.2-7 and p.5/l.3.
The specific claimed connections, i.e., more than 3000 connections per mm, absent any criticality, are only considered to be the “optimum” number of connections per mm disclosed by Aleksov that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired bandwidth, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a large number of connections is used, as already suggested by Aleksov/Saban.
Accordingly, since the applicants have not established the criticality (see next paragraph below) of the stated number of connections, it would have been obvious to one of ordinary skill in the art to use these values in the device of Aleksov/Saban to enable high bandwidth connection among the dies.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed number of connections or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov in view of Camarota (US 2018/0047663).
Regarding claim 4, Aleksov (see, e.g., fig. 1) shows most aspects of the instant invention including inter-die communications amongst the dies 102/104. He, however, fails to show buffers configure to buffer the inter-die communications. Camarota, in a similar device to Aleksov, teaches using buffers to convert high density bandwidth protocol of a FPGA die to a protocol compatible with the interposer. See, e.g., Camarota: ¶0038.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the buffer of Camarota in the FPGA architecture of Aleksov to enable communication between the high-density bandwidth protocol and the interposer-compatible protocol.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov/Camarota in view of Cheng (US 2020/0350321).
Regarding claim 5, Aleksov/Camarota do not expressly disclose that the IC dies include flip-flops. However, Cheng teaches FPGA circuitry that includes sequential elements such as flip-flops (registers) as part of the logic implementation (see, e.g., Cheng ¶¶ 49-50), describing logic elements that include combinational logic and associated registers/flip-flops.
It would have been obvious to one of ordinary skill in the art at the time of filing the invention to include flip-flops in the IC dies of Aleksov/Camarota because flip-flops are a known and conventional component included in FPGA circuitry, as taught by Cheng. Incorporating such known elements into the IC dies of Aleksov/Camarota would have been a routine design choice yielding predictable results. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov/Camarota/Saban.
Regarding claim 9, Aleksov (see, e.g., fig. 1) shows most aspect of the instant invention including a FPGA die 102. He, however, fails to show the device comprising a first die comprising a processor of the FPGA, a second die comprising a memory of the FPGA, a third die comprising input/output circuitry of the FPGA, and a fourth die comprising configurable logic of the FPGA. Aleksov teaches a multi-die package wherein the dies include FPGA dies (see, e.g., ¶ 0027). However, Aleksov treats the FPGA as a single die and does not teach the internal partitioning of FPGA functionality across separate constituent dies.
Camarota teaches an FPGA die comprises distinct and identifiable functional blocks including configurable logic blocks (CLBs) 102, memory blocks (BRAMs) 103, input/output blocks (IOBs) 104, configuration and clocking logic (CONFIG/CLOCKS) 105, digital signal processing (DSP) blocks 106, specialized I/O blocks 107, and a processor block PROC 110 (see, e.g., fig. 1 and ¶0025). Camarota further introduces the concept of tiles as modular separable architectural units of the FPGA, teaching that the FPGA resources are organized into tiles that implement key functionality ¶0025. This tiled modular architecture establishes that the functional blocks of the FPGA are architecturally separable units capable of being organized independently, providing the conceptual foundation for their distribution across separate dies. However, Camarota does not teach distributing these functional components across separate dies.
Saban teaches that an FPGA die may be distributed across multiple separate dies, referred to as SLR slices, on a silicon interposer, wherein each SLR slice implements a portion of the overall FPGA die functionality (see, e.g., p.2/ll.27-35 and p.4/ll.19-23). The slices or tiles are FPGA SLR dies implementing configurable logic, memory, DSP slices, and I/O interfaces, all interconnected through a silicon interposer. See, e.g., p.5/ll.5-8, p.6/l.2 and figs. 2 and 3. Saban teaches doing so to exceed the capacity and bandwidth offered by the larger device, but with the manufacturing and time-to-volume advantages of the smaller dies. See, e.g., Saban: p.4/ll.12-14 and p.2/ll.27-35.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a processor FPGA die, a memory FPGA die, an I/O FPGA die, and a configurable FPGA die in the dies of Aleksov, as suggested by Camarota and Saban, to exceed the capacity and bandwidth offered by the larger FPGA die but with the manufacturing and time-to-volume advantages of the smaller FPGA dies.
Response to Arguments
Applicant argues that Aleksov does not teach or suggest hybrid bonding connectors comprising metal pillars perpendicular to a surface of an interposer substrate, wherein a spacing between adjacent pillars is not greater than 10 micrometers. Applicant further argues that the close spacing of the hybrid bonding connectors is necessary to permit a distributed FPGA to communicate using a non-serialized protocol native to the FPGA.
The argument is not persuasive. As set forth above, Aleksov (see, e.g., fig. 1) expressly discloses a substrate 106 having high-density interconnects 116 and fine-pitch contacts 110. Aleksov further discloses fine pitch contacts having pitches ranging from 10 µm to 80 µm, with typical values ranging from 40 µm to 60 µm, and specifically discloses fine/line spacing of less than about 10 µm (see ¶0030). Aleksov therefore teaches the claimed high-density, closely spaced interconnect structure. Further, as shown in Fig. 1 and described in ¶¶0027-0028, contacts on dies 102 and 104 are coupled to corresponding contacts on substrate 106 through the substrate interconnect structure.
Applicant has not identified any structural distinction between the claimed hybrid bonding connectors and the fine-pitch contacts/interconnect structure disclosed by Aleksov. Rather, Applicant’s arguments are directed principally to the intended or functional manner in which the disclosed interconnections are used, i.e., communicating between FPGA dies using a non-serialized protocol native to the FPGA. As discussed above, Aleksov expressly contemplates that dies 102 and 104 may comprise FPGA devices (see ¶0027) and expressly provides high-density interconnects 116 for coupling the dies to one another (see ¶0028). Thus, the disclosed structure is capable of providing the recited inter-die communication.
Applicant’s reliance on the discussion in the specification concerning the advantages of using a non-serialized protocol does not distinguish the claimed structure from Aleksov. A recitation of a function or intended manner of operation does not distinguish an otherwise structurally identical prior-art device where the prior-art device is capable of performing the recited function. See MPEP §2114. Here, Aleksov’s FPGA dies and high-density interconnect structure are capable of communicating signals directly between the dies without requiring serialization/deserialization circuitry. Accordingly, the recitation that the dies communicate using a non-serialized protocol native to the FPGA does not impart a structural distinction over Aleksov.
Applicant further argues that Aleksov does not teach or suggest “an FPGA distributed over multiple IC dies” that communicates using a non-serialized protocol native to the FPGA. This argument is likewise not persuasive. Aleksov expressly identifies FPGAs as one type of integrated circuit device that may be used for dies 102 and 104 (¶0027), and expressly discloses coupling the dies through high-density interconnects 116 (¶0028). Thus, the combination of FPGA dies and inter-die high-density interconnections relied upon in the rejection is expressly contemplated by Aleksov. The additional recitation concerning the manner in which the FPGA dies communicate is a functional limitation that does not require a different physical structure than that already disclosed by Aleksov.
Moreover, Applicant’s argument appears to assume that the term “non-serialized protocol native to the FPGA” requires a particular physical implementation of the interconnect structure. The claims, however, recite the non-serialized native protocol as a manner of communication by the FPGA dies and do not recite particular structural circuitry for implementing such protocol. Applicant has not identified, and the claims do not require, any structural feature of the hybrid bonding connectors, interposer, metal layers, or dies that is absent from Aleksov as a result of the recited protocol.
Accordingly, Applicant’s arguments do not overcome the rejection. Aleksov discloses the claimed structural arrangement, including the interposer, metal layers, closely spaced connectors, dies disposed on the interposer, and inter-die connections, and further expressly contemplates FPGA dies. The recitation that the FPGA dies communicate using a non-serialized protocol native to the FPGA is a functional limitation that does not distinguish the claimed structure from the structure disclosed by Aleksov.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
August 23, 2026
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