Attorney’s Docket Number: 230371-US-ORG1
Filing Date: 6/26/2023
Inventors: Jain et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the election and amendment filed on 10/13/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 10/13/2025 in reply to the restriction in paper no. 4, mailed on 10/1/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Species Restriction
Applicant's election with traverse of the species reading on figures 5, 8 and 9, in the reply filed on 10/13/2025, is acknowledged. The traversal is on the grounds that there would not be a burden on the examiner to examine all the assemblies since they encompassed the elected claim and share common assembly features. This is not found persuasive because this argument conflates claims with species. Claims are not species. The fact that a single claim may encompass more than one species does not speak to whether the species themselves are distinct or whether their examination would require separate fields of search. The restriction requirement is directed to the species as inventions, not to the claims as drafted. Accordingly, the scope of the claims provides no basis for withdrawing the restriction. Also, the basis for a species restriction is not the presence of common features among the species, but rather their mutually exclusive features, i.e., the features that distinguish each species from the others and render them patentably distinct. The existence of shared features does not negate the existence of mutually exclusive features that define each species as a separate invention. As set forth in the previous restriction, because the species are different from one another and possess mutually exclusive characteristics, their examination would necessarily require different fields of search, including, for example, different search queries, classification areas, and prior art databases. Conducting separate searches across all species would impose a distinct and separate burden on the examiner, which is precisely the basis for the restriction.
Beyond the above argument, applicant has failed to provide any other reason leading to the conclusion that the species restriction should be withdrawn, and has not clearly admitted on the record that the non-elected species are not patentably distinct from the elected species. Absent such an admission or a compelling showing that no separate search or examination would be required, the restriction requirement is still deemed proper and is, therefore, made final.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character 704 has been used to designate both a circuit board and a package substrate (see, e.g., ¶0063/ll.3,8).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-19 are rejected under 35 U.S.C. 112(b), as being indefinite.
The claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention.
Claim 15 recites the limitation "the respective ID dies". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 10 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aleksov (US 2019/0198447).
Regarding claim 20, Aleksov (see, e.g., fig. 1) shows all aspects of the instant invention including an integrated circuit (IC) device comprising:
An interposer substrate 106 comprising:
A plurality of metal layers 114/116
A plurality of hybrid bonding connectors 114/116 exposed through a surface of the interposer, and
Electrical connections 114/116 between the connectors of the interposer and the metal layers, and
A plurality of field-programmable gate array (FPGA) chiplets 102/104 on the surface of the interposer
wherein:
The chiplets comprise respective connectors 108/110 exposed through surfaces of the chiplets in alignment with the connectors 114/116 of the interposer
The metal layers 114/116 are patterned to provide inter-die communications amongst the chiplets, and
The chiplets 102/104 are configured to communicate with one another via the connectors 110 of the chiplets and the connectors, metal layers, and connections 116 of the interposer 106
Regarding claim 15, Aleksov (see, e.g., fig. 1) shows all aspects of the instant invention including a device comprising:
An interposer substrate 106 comprising:
A plurality of metal layers 114/116
A plurality of connectors 114/116 exposed through a surface of the interposer, and
Connections 114/116 between the connectors of the interposer and the metal layer, and
Multiple IC dies 102/104 on the surface of the substrate
wherein:
The dies comprise respective connectors 108/110 exposed through surfaces of the dies in alignment with the connectors of the interposer
The metal layers 114/116 are patterned to provide inter-die communications amongst the dies
A first one 102 of the dies is configured to communicate with one 104 or more of the other dies via the connectors 110 of the dies and the connectors, connections, and metal layers 116 of the interposer 106
Regarding claim 18, Aleksov (see, e.g., ¶0027/ll.4-5 and fig. 1) shows the device wherein:
The connectors of the first die comprise connectors along an edge 110 and within a central region 108 of the surface of the die
The first die 102 comprises components of a FPGA and is configured to communicate with the one 104 or more of the other dies via the connectors 110 along the edge of the die
The metal layers 114 provide intra-die communications with the first die 102 through the connectors 108 within the central region of the die, and
The interposer 106 is configured to provide parameters to the first die 102 through the connectors 108 within the central region
Aleksov, however, fails to show that the first die uses a non-serialized protocol to communicate with the other dies, and that the parameters provided to the die are power, clock and configuration parameters. These limitations, however, are a description of the functions of the first die and the interposer. Under MPEP§2114, a structural limitation expressed functionally is satisfied by a prior art structure that is capable of performing the recited function. Aleksov (see, e.g., fig. 1) explicitly shows a first die 102 and an interposer 106.
The first die 102, by virtue of its inherent architecture, carries with it the capability to communicate using its native non-serialized protocol. The protocol capability is an intrinsic property of the first die. Therefore, the first die of Aleksov is inherently capable of communicating through its edge connectors using a native non-serialized protocol.
The interposer 106, by virtue of its inherent architecture, carries with it the capability to route clock, power and configuration signals to the first die 102 through its metal layer, electrical connections and hybrid connectors 114/116 (see, e.g., ¶0028 and fig. 1). The interposer of Aleksov, which already routes signals through the central connectors of the die, is, therefore, structurally capable of routing power, clock, and configuration signals through those same connectors. Routing signals is an intrinsic property of the interposer of Aleksov. Therefore, the interposer of Aleksov is inherently capable of providing clock, power and configuration signals through the central connectors of the first die.
Regarding claims 16, 17 and 19, see the comments above in paragraph 16 and 18 with respect to claim 18, which are considered repeated here.
Regarding claim 1, Aleksov (see, e.g., fig. 1) shows all aspects of the instant invention including a device comprising:
An interposer substrate 106 comprising:
A plurality of metal layers 114/116
A plurality of connectors 114/116 exposed through a surface of the interposer, and
Connections 114/116 between the connectors of the interposer and the metal layer, and
A FPGA distributed amongst multiple IC dies 102/104 on the surface of the substrate
wherein:
The dies 102/104 comprise respective connectors 108/110 exposed through surfaces of the dies in alignment with the connectors 114/116 of the interposer 106
The metal layers 114/116 are patterned to provide inter-die communications amongst the dies
The dies 102/104 are configured to communicate with one another via the connectors 110 of the dies and the connectors, connections, and metal layers 116 of the interposer
Regarding claim 7, Aleksov (see, e.g., fig. 1) shows the device wherein:
The connectors of the dies comprise connectors within central regions 108 of the dies, and
The metal layers 114/116 provide intra-die communications through the connectors 108 within the central regions of the dies
Regarding claim 8, see the comments above in paragraphs 21, 16, and 18 with respect to claims 7 and 18 which are considered repeated here.
Regarding claim 10, Aleksov (see, e.g., ¶0030) shows the connectors having pitches of 10 µm or less.
Regarding claim 2, Aleksov shows that the dies communicate with one another via the connectors 110 of the dies and the connectors, metal layer, and connections 116 of the interposer. See also the comments above in paragraphs 16-17 with respect to claim 18, which are considered repeated here.
Regarding claim 3, Aleksov (see, e.g., fig. 1) shows the device wherein:
The connectors of the dies comprise connectors along one or more edges 110 of the surfaces of the dies
The dies communicate with each other via the edge connectors 110 of the dies and the metal layers 116 and the connections of the interposer
See also the comments above in paragraphs 16-17 with respect to claim 18 which are considered repeated here.
Regarding claim 6, Aleksov shows the dies communicate with one another via the edge connectors 110 of the dies and the connections, and metal layers 116 of the interposer.
Synchronously in digital circuit design means that data transfer is governed by a common clock signal. Aleksov (see, e.g., ¶0027) teaches that the dies are FPGA, which are inherently synchronous. The limitation “communicate synchronously” is then considered functional language that describes an inherent property of the FPGA dies of Aleksov.
See also the comments above in paragraphs 16-17 with respect to claim 18 which are considered repeated here.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov in view Saban.
Regarding claims 11-14, Aleksov (see, e.g., fig. 1) shows the connectors of the interposer 116 and the dies 110, and the metal layers 116 of the interposer provide inter-die connections. He, however, fails to teach that they provide more than 3000 connections per mm. Saban, in a similar device to Aleksov, teaches that providing a large number of connections enables high-bandwidth connectivity between the dies by integrating massive quantities of resources within a single package. However, although Saban teaches providing more than 10,000 die-to-die connections, he fails to specify more than 3000 connections per mm. See, e.g., Saban: p.4/ll.2-7 and p.5/l.3.
The specific claimed connections, i.e., more than 3000 connections per mm, absent any criticality, are only considered to be the “optimum” number of connections per mm disclosed by Aleksov that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired bandwidth, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a large number of connections is used, as already suggested by Aleksov/Saban.
Accordingly, since the applicants have not established the criticality (see next paragraph below) of the stated number of connections, it would have been obvious to one of ordinary skill in the art to use these values in the device of Aleksov/Saban to enable high bandwidth connection among the dies.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed number of connections or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov in view of Camarota (US 2018/0047663).
Regarding claim 4, Aleksov (see, e.g., fig. 1) shows most aspects of the instant invention including inter-die communications amongst the dies 102/104. He, however, fails to show buffers configure to buffer the inter-die communications. Camarota, in a similar device to Aleksov, teaches using buffers to convert high density bandwidth protocol of a FPGA die to a protocol compatible with the interposer. See, e.g., Camarota: ¶0038.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the buffer of Camarota in the FPGA architecture of Aleksov to enable communication between the high-density bandwidth protocol and the interposer-compatible protocol.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov/Camarota in view of Cheng (US 2020/0350321).
Regarding claim 5, Aleksov/Camarota do not expressly disclose that the IC dies include flip-flops. However, Cheng teaches FPGA circuitry that includes sequential elements such as flip-flops (registers) as part of the logic implementation (see, e.g., Cheng ¶¶ 49-50), describing logic elements that include combinational logic and associated registers/flip-flops.
It would have been obvious to one of ordinary skill in the art at the time of filing the invention to include flip-flops in the IC dies of Aleksov/Camarota because flip-flops are a known and conventional component included in FPGA circuitry, as taught by Cheng. Incorporating such known elements into the IC dies of Aleksov/Camarota would have been a routine design choice yielding predictable results. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov/Camarota/Saban.
Regarding claim 9, Aleksov (see, e.g., fig. 1) shows most aspect of the instant invention including a FPGA die 102. He, however, fails to show the device comprising a first die comprising a processor of the FPGA, a second die comprising a memory of the FPGA, a third die comprising input/output circuitry of the FPGA, and a fourth die comprising configurable logic of the FPGA. Aleksov teaches a multi-die package wherein the dies include FPGA dies (see, e.g., ¶ 0027). However, Aleksov treats the FPGA as a single die and does not teach the internal partitioning of FPGA functionality across separate constituent dies.
Camarota teaches an FPGA die comprises distinct and identifiable functional blocks including configurable logic blocks (CLBs) 102, memory blocks (BRAMs) 103, input/output blocks (IOBs) 104, configuration and clocking logic (CONFIG/CLOCKS) 105, digital signal processing (DSP) blocks 106, specialized I/O blocks 107, and a processor block PROC 110 (see, e.g., fig. 1 and ¶0025). Camarota further introduces the concept of tiles as modular separable architectural units of the FPGA, teaching that the FPGA resources are organized into tiles that implement key functionality ¶0025. This tiled modular architecture establishes that the functional blocks of the FPGA are architecturally separable units capable of being organized independently, providing the conceptual foundation for their distribution across separate dies. However, Camarota does not teach distributing these functional components across separate dies.
Saban teaches that an FPGA die may be distributed across multiple separate dies, referred to as SLR slices, on a silicon interposer, wherein each SLR slice implements a portion of the overall FPGA die functionality (see, e.g., p.2/ll.27-35 and p.4/ll.19-23). The slices or tiles are FPGA SLR dies implementing configurable logic, memory, DSP slices, and I/O interfaces, all interconnected through a silicon interposer. See, e.g., p.5/ll.5-8, p.6/l.2 and figs. 2 and 3. Saban teaches doing so to exceed the capacity and bandwidth offered by the larger device, but with the manufacturing and time-to-volume advantages of the smaller dies. See, e.g., Saban: p.4/ll.12-14 and p.2/ll.27-35.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a processor FPGA die, a memory FPGA die, an I/O FPGA die, and a configurable FPGA die in the dies of Aleksov, as suggested by Camarota and Saban, to exceed the capacity and bandwidth offered by the larger FPGA die but with the manufacturing and time-to-volume advantages of the smaller FPGA dies.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
March 26, 2026
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