Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
This is a response to the election filed on 5/18/2026.
Applicant's arguments/remarks have been considered but are moot in view of the new ground(s) of rejection.
Species I (claims 1-13 and 20) = elected without traverse
Claims 14-19 = cancelled
Claims 21-16 = added
Claims 1-13 and 20-26 = remain pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 9-11, 20-22 and 24-26 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Castle (US 2019/0205491)
Regarding claim 1, the prior art discloses:
A method for circuit equivalence processing (abstract), comprising:
receiving a circuit design including a plurality of subsystems, each of the plurality of subsystems being implemented using at least one FPGA (fig 1);
analyzing, via one or more processors (fig 4-5), the plurality of subsystems for equivalence to identify at least two subsystems of the plurality of subsystems to be replaced with at least two replicated (fig 1 and related text) subsystems; and
generating a netlist (netlist is an inherent element file in circuit design for processing/ record/database/test/layout/check 1/simulation/synthesis/ placement/ routing/manufacturing/ verification, etc.) for the circuit design including the at least two replicated subsystems.
(Claim 2) wherein the at least two subsystems have different circuit structures and are identified to be equivalent based on logic of the at least two subsystems serving a common logic function (see functionally equivalent in fig 1).
(Claim 3) the at least two subsystems include at least a first subsystem and a second subsystem, at least one first circuit instance of the first subsystem being different than at least one second circuit instance of the second subsystem (fig 1-3 and related text); and identifying the at least two subsystems includes identifying whether the at least one first circuit instance and the at least one second circuit instance generate the same one or more outputs in response to one or more inputs (fig 1-3 and related text).
(Claim 5-6) wherein the at least two subsystems are identified to be equivalent:
based on a circuit description associated with the at least two subsystems being the same (fig 1-3 and related text);
by analyzing one or more inputs or one or more outputs of each subsystem of the at least two subsystems (fig 1-3 and related text);
(Claim 9) wherein the at least two subsystems includes at least a first subsystem and a second subsystem, the at least two subsystems being identified based on whether an entirety of the first subsystem is equivalent to a subset of the second subsystem (fig 1-3 and related text)
(Claim 10) wherein each of the at least two replicated subsystems replicates the second subsystem based on the entirety of the first subsystem being equivalent to the subset of the second subsystem(fig 1-3 and related text)
(Claim 11) wherein the at least two replicated subsystems include a first replicated subsystem to replace the first subsystem and a second replicated subsystem to replace the second subsystem, and wherein a circuit instance of the first replicated subsystem is deactivated (fig 1-3 and related text)
Claims 20-22 and 24-26 recited similar subject matter and are rejected for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 23 are rejected under 35 U.S.C. 103(a) as being unpatentable over Castle (US 2019/0205491) in view of Dennison (US 2008/028821) or Kim (US 2011/0237005)
Castle discloses substantially all the elements in the claims except graph isomorphism in claims 4, 23; however, this feature is disclosed by:
Dennison, paragraph 75, or
Kim, paragraph 4.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (in the instant application) to utilize graph isomorphism simply because one or more of the following reasons:
Dennison, paragraph 75: Isomorphic Graph algorithm to locate instances of sub-circuits in a larger design context that have the same topology as that of the corresponding sub-circuit, or
Kim, paragraph 4: layout and schematic netlists are compared by performing a graph isomorphism check to see if the netlists are equivalent.
Claims 12-13 are rejected under 35 U.S.C. 103(a) as being unpatentable over Castle (US 2019/0205491) in view of J et al (US 2023/0136353) or Fortier (US 2023/0336182).
Castle discloses substantially all the elements in the claims except the multiplexer, however, multiplexer is disclosed by:
J et al, paragraph 71, or
Fortier, paragraph 49.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (in the instant application) to utilize multiplexer simply because one or more of the following reasons:
J et al, paragraph 71: each replica circuit may be implemented in a known way, e.g., by using switches in the input paths to the multiplexer, or
Fortier, paragraph 49: replicated multiplexer (the replica circuit) may be connected in parallel with the multiplexer
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851
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