Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 10/16/25. Claims 9-15, 21-33 are pending in this application.
Restriction/Election
Applicants elect claims 9-15 and 21-33 for examination. Claims 1-8 and 16-20 have been canceled.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 21, 28 and 30 are rejected under 35 U.S.C. §102(a)(2) as being unpatentable over Jang US 20230021017 A1).
Regarding claim 9, Jang discloses a manufacturing method of a semiconductor storage cell structure (see fig 9, para [0046] disclosing storage cell), comprising: forming a first transistor (see transistor s/d Gate), which is a gate-all-around (GAA) structure (see 10/20 surrounds channels); and forming a second transistor on the first transistor (gates of two transistors 10/20), wherein an assistance gate layer is disposed above a storage node (see bridge structure 202). This office action notes that the modifier ‘above’ means vertically oriented noting that the claims do not claim orientation with respect to substrate or functionality, i.e. access to contacts.
Regarding claim 21, Jang discloses A manufacturing method of a semiconductor storage cell structure (see fig 9, para [0046] disclosing storage cell), comprising: forming a first transistor, which is a gate-all-around (GAA) structure (see 10 surrounds channel); and forming a second transistor on the first transistor (see formation of transistor with gate 20), wherein the first transistor has a vertical channel (see fig 9), and the second transistor has a horizontal channel (see horizontal portion of channel between 202).
Regarding claim 28, Jang discloses a manufacturing method of a semiconductor storage cell structure(see fig 9, para [0046] disclosing storage cell), comprising: forming a first transistor (see transistor associated with gate 10), which is a gate-all-around (GAA) structure (see 10 on both sides of channel); and forming a second transistor on the first transistor (see transistor associated with gate 20), wherein an assistance gate layer is disposed between a first gate layer of the first transistor and a second gate layer of the second transistor(see 202 positioned between 10 and 20).
Regarding claim 30, Jang discloses the manufacturing method of the semiconductor storage cell structure according to claim 28, wherein the step of forming the second transistor includes: forming the second gate layer connected to the first source layer(see gate of 10 is formed physically directly on materials connected with drain of 20); forming a second gate dielectric layer on the second gate layer(see 30); forming a second channel layer on the second gate dielectric layer (see channel for 10 and 20 formed against 30); forming a second source layer and a second drain layer on the second channel layer (see para [0044] disclosing semiconductor pillar 01 forms a source or drain, the first gate structure 10 is used as a gate of the first transistor, and the second gate structure 20 ), wherein the second drain layer is separated with the second source layer(see para [0044] disclosing semiconductor pillar 01 forms a source or drain, the first gate structure 10 is used as a gate of the first transistor, and the second gate structure 20 ); and forming the assistance gate layer (see 202) above the second channel layer and located between the second source layer and the second drain layer (see 202 is above 10 and in between 10 and 20).
Allowable Subject Matter
The cited art do not disclose:
wherein the step of forming the first transistor includes: forming a first gate layer on a base; forming a through hole passing through the first gate layer; forming a first gate dielectric layer at a side wall of the through hole, wherein the first gate dielectric layer is surrounded by the first gate layer; etching the base to form a concave; forming a first drain layer in the concave; forming a first channel layer in the through hole, wherein one side of the first channel layer is connected to the first drain layer, and the first channel layer is surrounded by the first gate dielectric layer; forming a first source layer connected to the first channel layer; and forming an insulating layer covering the first gate layer and the first gate dielectric layer and exposing the first source layer, as recited in claim 10. Claims 10 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 11-15 depend on claim 10 and would be allowable for the same.
wherein the step of forming the first transistor includes: forming a first gate layer on a base; forming a through hole passing through the first gate layer; forming a first gate dielectric layer at a side wall of the through hole, wherein the first gate dielectric layer is surrounded by the first gate layer; etching the base to form a concave; forming a first drain layer in the concave; forming a first channel layer in the through hole, wherein one side of the first channel layer is connected to the first drain layer, the first channel layer is surrounded by the first gate dielectric layer; forming a first source layer connected to the first channel layer; and forming an insulating layer covering the first gate layer and the first gate dielectric layer and exposing the first source layer, as recited in claim 22. Claims 23-27 depend from claim 21 and are also allowable.
wherein the step of forming the first transistor includes: forming the first gate layer on a base; forming a through hole passing through the first gate layer; forming a first gate dielectric layer at a side wall of the through hole, wherein the first gate dielectric layer is surrounded by the first gate layer; etching the base to form a concave; forming a first drain layer in the concave; forming a first channel layer in the through hole, wherein one side of the first channel layer is connected to the first drain layer, the first channel layer is surrounded by the first gate dielectric layer; forming a first source layer connected to the first channel layer; and forming an insulating layer covering the first gate layer and the first gate dielectric layer and exposing the first source layer, as recited in claim 29. Claims 31-33 depend from claim 29 and are allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893