Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 04/08/26. Claims 9-15, 21-33 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 21, 28 and 30 are rejected under 35 U.S.C. §103 as being unpatentable over Jang US 20230021017 A1) and further in view of Li (US 20230326965 A1).
Regarding claim 9, Jang discloses a manufacturing method of a semiconductor storage cell structure (see fig 9, para [0046] disclosing storage cell), comprising: forming a first transistor (see transistor s/d Gate), which is a gate-all-around (GAA) structure (see 10/20 surrounds channels); and forming a second transistor on the first transistor (gates of two transistors 10/20), wherein an assistance gate layer is disposed above a storage node (see bridge structure 202). This office action notes that the modifier ‘above’ means vertically oriented noting that the claims do not claim orientation with respect to substrate or functionality, i.e. access to contacts.
However, Jang does not disclose a second gate dielectric. However, Li, at least at paras [0064] discloses a second dielectric in a GAA arrangement. Jang and Li are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Jang and Li. Jang and Li may be combined by forming the device of Jang to have two gate dielectric layers, in order to adjust to higher operating voltages, see para [0066] of Li.
Regarding claim 21, Jang discloses A manufacturing method of a semiconductor storage cell structure (see fig 9, para [0046] disclosing storage cell), comprising: forming a first transistor, which is a gate-all-around (GAA) structure (see 10 surrounds channel); and forming a second transistor on the first transistor (see formation of transistor with gate 20), wherein the first transistor has a vertical channel (see fig 9), and the second transistor has a horizontal channel (see horizontal portion of channel between 202).
However, Jang does not disclose a second gate dielectric. However, Li, at least at paras [0064] discloses a second dielectric in a GAA arrangement. Jang and Li are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Jang and Li. Jang and Li may be combined by forming the device of Jang to have two gate dielectric layers, in order to adjust to higher operating voltages, see para [0066] of Li.
Regarding claim 28, Jang discloses a manufacturing method of a semiconductor storage cell structure(see fig 9, para [0046] disclosing storage cell), comprising: forming a first transistor (see transistor associated with gate 10), which is a gate-all-around (GAA) structure (see 10 on both sides of channel); and forming a second transistor on the first transistor (see transistor associated with gate 20), wherein an assistance gate layer is disposed between a first gate layer of the first transistor and a second gate layer of the second transistor(see 202 positioned between 10 and 20).
However, Jang does not disclose a second gate dielectric. However, Li, at least at paras [0064] discloses a second dielectric in a GAA arrangement. Jang and Li are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Jang and Li. Jang and Li may be combined by forming the device of Jang to have two gate dielectric layers, in order to adjust to higher operating voltages, see para [0066] of Li.
Regarding claim 30, Jang and Li disclose the manufacturing method of the semiconductor storage cell structure according to claim 28, wherein the step of forming the second transistor includes: forming the second gate layer connected to the first source layer(see gate of 10 is formed physically directly on materials connected with drain of 20); forming a second gate dielectric layer on the second gate layer(see para [0066] of Li); forming a second channel layer on the second gate dielectric layer (see channel for 10 and 20 formed against 30); forming a second source layer and a second drain layer on the second channel layer (see para [0044] disclosing semiconductor pillar 01 forms a source or drain, the first gate structure 10 is used as a gate of the first transistor, and the second gate structure 20 ), wherein the second drain layer is separated with the second source layer(see para [0044] disclosing semiconductor pillar 01 forms a source or drain, the first gate structure 10 is used as a gate of the first transistor, and the second gate structure 20 ); and forming the assistance gate layer (see 202) above the second channel layer and located between the second source layer and the second drain layer (see 202 is above 10 and in between 10 and 20).
Allowable Subject Matter
The cited art do not disclose:
wherein the step of forming the first transistor includes: forming a first gate layer on a base; forming a through hole passing through the first gate layer; forming a first gate dielectric layer at a side wall of the through hole, wherein the first gate dielectric layer is surrounded by the first gate layer; etching the base to form a concave; forming a first drain layer in the concave; forming a first channel layer in the through hole, wherein one side of the first channel layer is connected to the first drain layer, and the first channel layer is surrounded by the first gate dielectric layer; forming a first source layer connected to the first channel layer; and forming an insulating layer covering the first gate layer and the first gate dielectric layer and exposing the first source layer, as recited in claim 10. Claims 10 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 11-15 depend on claim 10 and would be allowable for the same.
wherein the step of forming the first transistor includes: forming a first gate layer on a base; forming a through hole passing through the first gate layer; forming a first gate dielectric layer at a side wall of the through hole, wherein the first gate dielectric layer is surrounded by the first gate layer; etching the base to form a concave; forming a first drain layer in the concave; forming a first channel layer in the through hole, wherein one side of the first channel layer is connected to the first drain layer, the first channel layer is surrounded by the first gate dielectric layer; forming a first source layer connected to the first channel layer; and forming an insulating layer covering the first gate layer and the first gate dielectric layer and exposing the first source layer, as recited in claim 22. Claims 23-27 depend from claim 21 and are also allowable.
wherein the step of forming the first transistor includes: forming the first gate layer on a base; forming a through hole passing through the first gate layer; forming a first gate dielectric layer at a side wall of the through hole, wherein the first gate dielectric layer is surrounded by the first gate layer; etching the base to form a concave; forming a first drain layer in the concave; forming a first channel layer in the through hole, wherein one side of the first channel layer is connected to the first drain layer, the first channel layer is surrounded by the first gate dielectric layer; forming a first source layer connected to the first channel layer; and forming an insulating layer covering the first gate layer and the first gate dielectric layer and exposing the first source layer, as recited in claim 29. Claims 31-33 depend from claim 29 and are allowable.
Response to Arguments
Applicant has amended claims to recite additional features. This office action now cites to Li as disclosing these features. Thus, applicant’s assertions are now moot.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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