DETAILED ACTION
This office action is in response to the application filed on 6/28/2023. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/17/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 recites the limitation "the die" in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required. For purpose of examination, the examiner has interpreted the limitation to read as “the first die.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-8, 10, 12-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen (US 12,125,820).
With respect to Claim 1, Chen shows (Fig 8-14) all aspects of the current invention including a method of producing a three-dimensional (3D) die stack, comprising:
stacking a first die (310 right) on top of a second die (210), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization 314,318 right) of the first die aligns with a second routing sub-region (metallization 214,218 right) of the second die;
stacking a third die (310 left) on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region (metallization 314,318 left) of the third die aligns with a fourth routing sub-region (metallization 214,218 left) of the second die
With respect to Claim 2, Chen shows (Fig 8-14) wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region
With respect to Claim 3, Chen shows (Fig 8-14) wherein the first die does not directly communicate with the third die
With respect to Claim 4, Chen shows (Fig 8-14) wherein the first die, the second die, and the third die comprise programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region comprise fabric sub-regions.
With respect to Claim 5, Chen shows (Fig 8-14) further comprising stacking a fourth die (410) on top of the first die and the third die, wherein a fifth routing sub-region (metallization 418 right) of the fourth die aligns with at least a portion of the second routing sub-region of the second die, and a sixth routing sub-region (metallization 418 left) of the fourth die aligns with at least a portion of the fourth routing sub-region of the second die, and wherein the fifth routing sub-region of the fourth die communicates with the second routing sub-region via the first routing sub-region of the first die, and the sixth routing sub-region of the fourth die communicates with the fourth routing sub-region via the third routing sub-region of the third die.
With respect to Claim 6, Chen shows (Fig 21-24) an embodiment further comprising stacking the second die (210) on an input/output (I/O) die (110; in this embodiment, 110 is a device die which may include an Input-Output (IO) die), wherein the second die is offset from the I/O die in at least one of the x-direction and the y-direction, and a fifth routing sub-region (metallization 118 right) of the I/O die aligns with the second routing sub-region of the second die
With respect to Claim 7, Chen shows (Fig 8-14) wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application- specific integrated circuit (ASIC) die, and a memory die.
With respect to Claim 8, Chen shows (Fig 8-14) wherein one or more die layers (230) are disposed between the first die and the second die.
With respect to Claim 10, Chen shows (Fig 8-14) wherein the first die is included in a first wafer (232) comprising a first plurality of dice, and the second die is included in a second wafer (332) comprising a second plurality of dice, wherein each die included in the first plurality of dice is offset from each die included in the second plurality of dice in at least one of the x-direction and the y-direction, and at least one routing sub-region of each die included in the first plurality of dice aligns with at least one routing sub-region of a die included in the second plurality of dice.
With respect to Claim 12, Chen shows (Fig 8-14) wherein the first routing sub-region comprises a first field-programmable gate array (FPGA) fabric, the second routing sub-region comprises a second FPGA fabric, the third routing sub-region comprises a third FPGA fabric, and the fourth routing sub-region comprises a fourth FPGA fabric.
With respect to Claim 13, Chen shows (Fig 14) all aspects of the current invention including a three-dimensional (3D) die stack, comprising:
a first die (310 right) stacked on top of a second die (210), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization 314,318 right) of the first die aligns with a second routing sub-region (metallization 214,218 right) of the second die;
a third die (310 left) stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region (metallization 314,318 left) of the third die aligns with a fourth routing sub-region (metallization 214,218 left) of the second die
With respect to Claim 14, Chen shows (Fig 14) wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region
With respect to Claim 15, Chen shows (Fig 14) wherein the first die does not directly communicate with the third die
With respect to Claim 16, Chen shows (Fig 14) wherein the first die, the second die, and the third die comprise programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region comprise fabric sub-regions.
With respect to Claim 17, Chen shows (Fig 14) wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application- specific integrated circuit (ASIC) die, and a memory die.
With respect to Claim 18, Chen shows (Fig 14) wherein one or more die layers (230) are disposed between the first die and the second die
With respect to Claim 19, Chen shows (Fig 14) wherein the die is included in a first wafer (232) comprising a first plurality of dice, and the second die is included in a second wafer (332) comprising a second plurality of dice, wherein each die included in the first plurality of dice is offset from each die included in the second plurality of dice in at least one of the x-direction and the y-direction, and at least one routing sub-region of each die included in the first plurality of dice aligns with at least one routing sub-region of a die included in the second plurality of dice.
Claim 1-4, 7-8, 12-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilkerson (US 10,573,630).
With respect to Claim 1, Wilkerson shows (Fig 7) all aspects of the current invention including a method of producing a three-dimensional (3D) die stack, comprising:
stacking a first die (200 right) on top of a second die (100), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization pad on active side of die 200 right) of the first die aligns with a second routing sub-region (metallization 708 right side) of the second die;
stacking a third die (200 left) on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub- region (metallization pad on active side of die 200 left) of the third die aligns with a fourth routing sub- region (metallization 708 left side) of the second die
With respect to Claim 2, Wilkerson shows (Fig 7) wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region
With respect to Claim 3, Wilkerson shows (Fig 7) wherein the first die does not directly communicate with the third die
With respect to Claim 4, Wilkerson shows (Fig 7) wherein the first die, the second die, and the third die comprise programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region comprise fabric sub-regions
With respect to Claim 7, Wilkerson shows (Fig 7) wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application- specific integrated circuit (ASIC) die, and a memory die
With respect to Claim 8, Wilkerson shows (Fig 7) wherein one or more die layers are disposed between the first die and the second die
With respect to Claim 12, Wilkerson shows (Fig 7) wherein the first routing sub-region comprises a first field- programmable gate array (FPGA) fabric, the second routing sub-region comprises a second FPGA fabric, the third routing sub-region comprises a third FPGA fabric, and the fourth routing sub-region comprises a fourth FPGA fabric.
With respect to Claim 13, Wilkerson shows (Fig 7) all aspects of the current invention including a three-dimensional (3D) die stack, comprising:
a first die (200 right) stacked on top of a second die (100), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization pad on active side of die 200 right) of the first die aligns with a second routing sub-region (metallization 708 right side) of the second die
a third die (200 left) stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region (metallization pad on active side of die 200 left) of the third die aligns with a fourth routing sub-region (metallization 708 left side) of the second die
With respect to Claim 14, Wilkerson shows (Fig 7) wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region
With respect to Claim 15, Wilkerson shows (Fig 7) wherein the first die does not directly communicate with the third die
With respect to Claim 16, Wilkerson shows (Fig 7) wherein the first die, the second die, and the third die comprise programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region comprise fabric sub-regions
With respect to Claim 17, Wilkerson shows (Fig 7) wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die
With respect to Claim 18, Wilkerson shows (Fig 7) wherein one or more die layers are disposed between the first die and the second die
Claim 1-3, 7-8, 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2019/0148276).
With respect to Claim 1, Chen shows (Fig 1-15) all aspects of the current invention including a method of producing a three-dimensional (3D) die stack, comprising:
stacking a first die (114 right) on top of a second die (160), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization of 120 connected to pad 126b right) of the first die aligns with a second routing sub-region (metallization of 163 connected to pad 168) of the second die;
stacking a third die (114 left) on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub- region (metallization of 120 connected to pad 126b left) of the third die aligns with a fourth routing sub- region (metallization of 163 connected to pad 168) of the second die
With respect to Claim 2, Chen shows (Fig 1-15) wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region.
With respect to Claim 3, Chen shows (Fig 1-15) wherein the first die does not directly communicate with the third die
With respect to Claim 7, Chen shows (Fig 1-15) wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application- specific integrated circuit (ASIC) die, and a memory die.
With respect to Claim 8, Chen shows (Fig 1-15) wherein one or more die layers are disposed between the first die and the second die
With respect to Claim 12, Chen shows (Fig 1-15) wherein the first routing sub-region comprises a first field- programmable gate array (FPGA) fabric, the second routing sub-region comprises a second FPGA fabric, the third routing sub-region comprises a third FPGA fabric, and the fourth routing sub-region comprises a fourth FPGA fabric.
With respect to Claim 13, Chen shows (Fig 1-15) all aspects of the current invention including a three-dimensional (3D) die stack, comprising:
a first die (114 right) stacked on top of a second die (160), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization of 120 connected to pad 126b right) of the first die aligns with a second routing sub-region (metallization of 163 connected to pad 168) of the second die
a third die (114 left) stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region (metallization of 120 connected to pad 126b left) of the third die aligns with a fourth routing sub-region (metallization of 163 connected to pad 168) of the second die
With respect to Claim 14, Chen shows (Fig 1-15) wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region
With respect to Claim 15, Chen shows (Fig 1-15) wherein the first die does not directly communicate with the third die.
With respect to Claim 16, Chen shows (Fig 1-15) wherein the first die, the second die, and the third die comprise programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing sub-region comprise fabric sub-regions
With respect to Claim 17, Chen shows (Fig 1-15) wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 12,125,820) in view of Camarota (US 11,189,338).
With respect to Claim 9, Chen shows (Fig 8-14) most aspects of the current invention including the bonding of the first die on top of the second die and the third die on top of the second die is done through method steps of stacking the first die on top of the second die comprises bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises bonding a third wafer comprising the third die to the second wafer, by hybrid bonding (i.e. direct metal-to-metal bonding or fusion bonding).
However, Chen does not explicitly disclose wherein the bonding method is hybrid oxide bonding.
On the other hand, and in the same field of endeavor, Camarota teaches (Fig 2) a method of producing a three-dimensional (3D) die stack comprising a chip stack including multiple programmable IC chips (e.g., programmable IC chips 204, 212, 214, 216), wherein the chips can be stacked on each other and bonded by a hybrid oxide to oxide method. Camarota teaches this allows a device in which flexibility in using a chip having an interface that is configurable to implement multi-rank HBM can be achieved.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have stacking the first die on top of the second die comprises hybrid oxide bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises hybrid oxide bonding a third wafer comprising the third die to the second wafer, in the device of Chen, as taught by Camarota allowing a device in which flexibility in using a chip having an interface that is configurable to implement multi-rank HBM can be achieved.
Additionally, one of ordinary skill in the semiconductor manufacturing art would have known hybrid oxide bonding is used as a bonding method to bond dies together. Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have stacking the first die on top of the second die comprises hybrid oxide bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises hybrid oxide bonding a third wafer comprising the third die to the second wafer, in the device of Chen, as taught by Camarota because such method is known in the semiconductor manufacturing art for bonding dies together, as suggested by Camarota, and applying a known method step for its conventional purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claims 9, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wilkerson (US 10,573,630) in view of Camarota (US 11,189,338).
With respect to Claim 9, Wilkerson shows (Fig 7) most aspects of the current invention. Furthermore, Wilkerson shows the bonding of the first die on top of the second die and the third die on top of the second die through method steps of stacking the first die on top of the second die comprises bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises bonding a third wafer comprising the third die to the second wafer, by direct bonding or a different bonding technique.
However, Wilkerson does not show wherein the bonding method is hybrid oxide bonding.
On the other hand, and in the same field of endeavor, Camarota teaches (Fig 2) a method of producing a three-dimensional (3D) die stack comprising a chip stack including multiple programmable IC chips (e.g., programmable IC chips 204, 212, 214, 216), wherein the chips can be stacked on each other and bonded by a hybrid oxide to oxide method. Camarota teaches this allows a device in which flexibility in using a chip having an interface that is configurable to implement multi-rank HBM can be achieved.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have stacking the first die on top of the second die comprises hybrid oxide bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises hybrid oxide bonding a third wafer comprising the third die to the second wafer, in the device of Wilkerson, as taught by Camarota allowing a device in which flexibility in using a chip having an interface that is configurable to implement multi-rank HBM can be achieved.
Additionally, one of ordinary skill in the semiconductor manufacturing art would have known hybrid oxide bonding is used as a bonding method to bond dies together. Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have stacking the first die on top of the second die comprises hybrid oxide bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises hybrid oxide bonding a third wafer comprising the third die to the second wafer, in the device of Wilkerson, as taught by Camarota because such method is known in the semiconductor manufacturing art for bonding dies together, as suggested by Camarota, and applying a known method step for its conventional purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 11, Wilkerson shows (Fig 7) most aspects of the current invention. However, Wilkerson does not show wherein a pitch of electrical connections between (i) a bottom of the first die and a top of the second die, and (ii) between a bottom of the third die and the top of the second die is less than 5 microns.
On the other hand, and in the same field of endeavor, Camarota teaches (Fig 2) a method of producing a three-dimensional (3D) die stack comprising a chip stack including multiple programmable IC chips (e.g., programmable IC chips 204, 212, 214, 216), wherein the chips can be stacked on each other, and wherein a pitch of electrical connections between (i) a bottom of the first die and a top of the second die, and (ii) between a bottom of the third die and the top of the second die is less than 5 microns.
Regarding claim 11, the courts have held that differences in the pitches will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such pitches are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the pitches and similar pitches are known in the art (see e.g. Camarota), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Wilkerson.
Criticality: The specification contains no disclosure of either the critical nature of the claimed pitches or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Camarota (US 11,189,338) in view of Chen (US 12,125,820).
With respect to Claim 20, Camarota shows (Fig 1-2) most aspects of the current invention including a computing system, comprising a memory (106; memory controllers); and a three-dimensional (3D) die stack (130; one or more chip stacks, each including multiple memory chips) coupled to the memory.
However, Camarota does not show wherein the three-dimensional (3D) die stack comprising: a first die stacked on top of a second die, wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die; and a third die stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.
On the other hand, and in the same field of endeavor, Chen teaches (Fig 14) a three-dimensional (3D) die stack, comprising:
a first die (310 right) stacked on top of a second die (210), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization 314,318 right) of the first die aligns with a second routing sub-region (metallization 214,218 right) of the second die;
a third die (310 left) stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region (metallization 314,318 left) of the third die aligns with a fourth routing sub-region (metallization 214,218 left) of the second die
Chen teaches forming a three-dimensional (3D) package containing through-dielectric vias in gap-filling regions that encircle the device dies, and the through-dielectric vias replace some of the otherwise through-semiconductor vias, and hence have lower resistivity.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the three-dimensional (3D) die stack comprising: a first die stacked on top of a second die, wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die; and a third die stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die in the device of Camarota, as taught by Chen to form a three-dimensional (3D) package containing through-dielectric vias in gap-filling regions that encircle the device dies, and the through-dielectric vias replace some of the otherwise through-semiconductor vias, and hence have lower resistivity.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Camarota (US 11,189,338) in view of Wilkerson (US 10,573,630).
With respect to Claim 20, Camarota shows (Fig 1-2) most aspects of the current invention including a computing system, comprising a memory (106; memory controllers); and a three-dimensional (3D) die stack (130; one or more chip stacks, each including multiple memory chips) coupled to the memory.
However, Camarota does not show wherein the three-dimensional (3D) die stack comprising: a first die stacked on top of a second die, wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die; and a third die stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.
On the other hand, and in the same field of endeavor, Wilkerson teaches (Fig 7) a three-dimensional (3D) die stack, comprising:
a first die (200 right) stacked on top of a second die (100), wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region (metallization pad on active side of die 200 right) of the first die aligns with a second routing sub-region (metallization 708 right side) of the second die
a third die (200 left) stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region (metallization pad on active side of die 200 left) of the third die aligns with a fourth routing sub-region (metallization 708 left side) of the second die
Wilkerson teaches offsetting the first and third die with respect to the first die in a three-dimensional integrated circuit structure provides space to position a lower thermal resistance path structure directly on top of a region of the first die having a higher power density.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the three-dimensional (3D) die stack comprising: a first die stacked on top of a second die, wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die; and a third die stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die in the device of Camarota, as taught by Wilkerson because offsetting the first and third die with respect to the first die in a three-dimensional integrated circuit structure provides space to position a lower thermal resistance path structure directly on top of a region of the first die having a higher power density.
Conclusion
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/Q.A.B/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814