DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the device of invention I, claims 1-13 in the reply filed on 9/24/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 12-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by TANAKA (US 20230307535).
Regarding claim 1, TANAKA discloses a semiconductor device, comprising:
a substrate (substrate 1, see fig 1, para 25), having a first conductivity type (1 is n-type, see fig 4, para 25) and comprising a cell region (the region of the device inside 10a comprising the transistor cells around electrodes 10, see fig 1-4, para 38) and a termination region (the region of the device not inside 10a, see fig 1-4, para 38);
a trench (the trench in which 10 and 11 are disposed, see fig 4, para 31), disposed in the substrate and located in the cell region;
a gate electrode (gate electrode 10, see fig 4, para 31), disposed in the trench;
a shielding doped region, having a second conductivity type, disposed in the substrate and located directly below the trench (p+ type region 4 which is directly below 11 in the trench, see fig 4, para 31);
a buried guard ring, having the second conductivity type, disposed in the substrate and located in the termination region (p+ type region 5a which is outside 10a, see fig 4, para 38),
wherein the buried guard ring and the shielding doped region are at the same depth in the substrate (both 4 and 5a are located at the depth of the bottom surface of 1b, see fig 4); and
a junction termination extension structure (the portions of 2, 6a and 6 outside 10a, see fig 4, para 38), having the second conductivity type (2, 6a and 6 are p-type, see fig 4), disposed in the substrate (2, 6 and 6 are in 1, see fig 4), located directly above the buried guard ring, (2 is directly above 5a, see fig 4) and separated from the buried guard ring (5 and 2 are separated by 1b, see fig 4).
Regarding claim 2, TANAKA discloses the semiconductor device of claim 1, wherein the junction termination extension structure comprises an inner doped region (6a, see fig 4, para 38) and a plurality of laterally separated outer doped regions (regions 6, see fig 5, para 25), and
the inner doped region and the plurality of laterally separated outer doped regions have the same doping concentration (6a and 6 are all p- regions, see fig 4).
Regarding claim 3, TANAKA discloses the semiconductor device of claim 2, wherein a vertical projection area of the plurality of laterally separated outer doped regions is outside a vertical projection area of the buried guard ring (6 and 5a do not overlap along the vertical z-direction, see fig 4).
Regarding claim 4, TANAKA discloses the semiconductor device of claim 2, wherein an outermost edge of the inner doped region is farther away from the cell region than an outermost edge of the buried guard ring (the outermost right edge of 6a is further from the center of the device to the left of fig 4 than is the outermost right edge of 5a, see fig 4).
Regarding claim 12, TANAKA discloses the semiconductor device of claim 1, wherein the shielding doped region and the buried guard ring are laterally separated from each other (4 and 5a are separated laterally, see fig 4), and
the buried guard ring and the shielding doped region have the same thickness (4 and 5 have a same thickness, see fig 4).
Regarding claim 13, TANAKA discloses the semiconductor device of claim 1, wherein both the buried guard ring and the junction termination extension structure are electrically coupled to a source electrode or a ground terminal (the buried guard ring 5a is coupled to source electrode 22 by 4a and 2, and the junction termination extension region 2 is directly coupled to 22, see fig 4).
Claim(s) 1 and 5-7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KINOSHITA (US 20220344475).
Regarding claim 1, KINOSHITA discloses a semiconductor device, comprising:
a substrate, having a first conductivity type (n-type substrate 40, see fig 2, para 34) and comprising a cell region (cell region 1a, see fig2, para 35), and a termination region (regions 1b and 2, see fig 2, para 43);
a trench, disposed in the substrate and located in the cell region (trench 16, see fig 2, para 68);
a gate electrode, disposed in the trench (fig 2, 18, para 38);
a shielding doped region, having a second conductivity type, disposed in the substrate and located directly below the trench (p+ region 21 below 18, see fig 2, para 41);
a buried guard ring, having the second conductivity type, disposed in the substrate and located in the termination region (p-type regions 22a and 31 in 40, see fig 2, para 48),
wherein the buried guard ring and the shielding doped region are at the same depth in the substrate (a horizontal line can be drawn through 21 that passes through 22a and 31, see fig 2); and
a junction termination extension structure, having the second conductivity type, disposed in the substrate, located directly above the buried guard ring, and separated from the buried guard ring (p++ region 15a, which is above and separated from 22a, see fig 2, para 44).
Regarding claim 5, KINOSHITA discloses the semiconductor device of claim 1, wherein the buried guard ring comprises a plurality of laterally separated ring-shaped doped regions (there are a plurality of regions 31 which are laterally separated from each other with portions of 12 between them, see fig 2), and
doping concentrations of the plurality of laterally separated ring-shaped doped regions are the same as a doping concentration of the shielding doped region (31 and 21 are formed in the same ion implantation process, and will thus have the same concentration, see fig 4, para 71).
Regarding claim 6, KINOSHITA discloses the semiconductor device of claim 5, wherein a plurality of spacing between the plurality of laterally separated ring-shaped doped regions are gradually increased in a direction from the cell region to the termination region (the interval x_n between regions 31 increases arithmetically with increasing distance from the center, see para 51).
Regarding claim 7, KINOSHITA discloses the semiconductor device of claim 5, wherein the plurality of laterally separated ring-shaped doped regions have the same width (all regions 31 have the same width, see para 49).
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SAITO (US 20160329422).
Regarding claim 1, SAITO discloses a semiconductor device, comprising:
a substrate, having a first conductivity type (n-type semiconductor 12, see fig 1-2, para 30) and comprising a cell region (fig 1-2, 20, para 30) and a termination region (fig 1-2, 50, para 30);
a trench, disposed in the substrate and located in the cell region (gate trench 34, see fig 1-2, para 32);
a gate electrode (fig 2, 34c, para 38), disposed in the trench;
a shielding doped region, having a second conductivity type, disposed in the substrate and located directly below the trench (fig 2, 32, para 21);
a buried guard ring, having the second conductivity type, disposed in the substrate and located in the termination region (the p-regions 56, see fig 2, para 42),
wherein the buried guard ring and the shielding doped region are at the same depth in the substrate (a horizontal Ine can be drawn through 32 and 56, see fig 2); and
a junction termination extension structure, having the second conductivity type, disposed in the substrate, located directly above the buried guard ring, and separated from the buried guard ring (regions 51 are located above and separated from 56, see fig 2, para 40).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over SAITO (US 20160329422) in view of KINOSHITA (US 20220344475).
Regarding claim 5, SAITO discloses the semiconductor device of claim 1.
SAITO further discloses a device, wherein the buried guard ring comprises a plurality of laterally separated ring-shaped doped regions (there are a plurality of doped regions 56 which are laterally separated by portions of 28, see fig 2, para 42).
SAITO fails to explicitly disclose a device wherein doping concentrations of the plurality of laterally separated ring-shaped doped regions are the same as a doping concentration of the shielding doped region.
KINOSHITA teaches a device wherein doping concentrations of the plurality of laterally separated ring-shaped doped regions are the same as a doping concentration of the shielding doped region (31 and 21 are formed in the same ion implantation process, and will thus have the same concentration, see fig 4, para 71).
SAITO and KINOSHITA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SAITO with the specific doping concentrations of KINOSHITA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SAITO with the specific doping concentrations of KINOSHITA in order to stably ensure the breakdown voltage (see KINOSHITA para 32).
Regarding claim 8, SAITO and KINOSHITA disclose the semiconductor device of claim 5.
SAITO further discloses a device, further comprising a plurality of trench isolation structures disposed in the substrate and located in the termination region (fig 1-2, 53, para 41),
wherein the plurality of trench isolation structures are correspondingly disposed directly above the plurality of laterally separated ring-shaped doped regions (53 are above 56, see fig 2, para 41).
Regarding claim 9, SAITO and KINOSHITA disclose the semiconductor device of claim 8.
SAITO further discloses a device, wherein the plurality of trench isolation structures pass through the junction termination extension structure (53 passes through 51, see fig 2, para 41), and
bottom surfaces of the plurality of trench isolation structures are at the same level in the height with a bottom surface of the trench (bottom surfaces of 34 and 53 are located at a depth into 12, see fig 2, para 42).
Regarding claim 10, SAITO and KINOSHITA disclose the semiconductor device of claim 1.
SAITO further discloses a device, wherein a doping concentration of the junction termination extension structure is lower than a doping concentration of the buried guard ring (26 is a low-concentration region and 56 are high-concentration, see fig 2, para 63).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over TANAKA (US 20230307535) in view of SUZUKI (US 20090200559).
Regarding claim 11, TANAKA discloses the semiconductor device of claim 1.
TANAKA fails to explicitly disclose a device, wherein a thickness of the junction termination extension structure is greater than a thickness of the buried guard ring.
SUZUKI teaches a device, wherein a thickness of the junction termination extension structure is greater than a thickness of the buried guard ring (the base region 303 which is part of the junction extension region can have a thickness of 2 microns, and part of the guard ring 316 can have a thickness of 0.7 microns, see fig 31a, para 204 and 217).
TANAKA and SUZUKI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TANAKA with the specific layer thicknesses of SUZUKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TANAKA with the specific layer thicknesses of SUZUKI in order to increase the channel mobility (see SUZUKI para 159).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811