DETAILED ACTION
Claims 1-22 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of prior-filed applications under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/562,003 and grandparent application 17/465,949 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
The examiner notes that applicant has cited NPL without providing relevant page numbers. While the NPL has been considered, please cite relevant page numbers for any NPL cited in the future, as required by 37 CFR 1.98(b)(5), to ensure consideration thereof.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
In paragraphs 1-3, applicant lists related applications. Patent numbers must be inserted for any application that has resulted in a patent. While none of the applications appear to have been patented at the time of drafting this Office Action, this note will serve as a reminder, until allowance of this application, to insert patent numbers as related applications issue.
The disclosure is objected to because of the following informalities:
The first sentence of paragraph 52 is a duplicate of the first sentence of paragraph 51. Thus, the duplicate could be deleted.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 1, replace “processing comprising:” with --processing, the method comprising:-- so that the steps are explicitly tied to the method and not potentially to the parallel processing.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 17, “wherein the compressed control words are decompressed before being consumed by a next unit”. This next unit, per paragraph 35 of the specification, includes a controller. However, the controller is a generic black box whose specific structure is undisclosed. As such, the examiner is unable to interpret the claim according to structure(s) in applicant’s specification. Consequently, broadest reasonable interpretation is taken and 112(a)/(b) rejections appear below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. Possession is shown by describing the claimed invention and, for means+function-type claims, this necessitates describing the specific structure to which the claimed means are limited. As described above in the “Claim Interpretation” section, since applicant has not disclosed specific structure for the next unit of claim 17 (to perform the consuming), as required for 112(f) interpretation, the claimed next unit has not been adequately described and, hence, possession thereof has not been established.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 17, the claimed next unit for consuming decompressed control words invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described in the “Claim Interpretation” section above, the written description fails to disclose the corresponding structure, material, or acts for performing the claimed consuming function and to clearly link the structure, material, or acts to the function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Referring to claims 18-20, the term “wide” is a relative term which renders the claims indefinite. The term is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, the examiner is not clear on where the line is drawn between wide and not wide. For purposes of prior art examination, anything larger than 1 bit will be deemed wide.
Claims 19-20 are also rejected due to their dependence on an indefinite claim.
Claim 21 is indefinite because the examiner is unclear as to how the one or more processors in lines 2-3 both (1) access a 2D array of compute elements, which implies that the array is separate from the one or more processors, and (2) execute instructions within the array of compute elements, which seems to imply that the one or more processors are within the array. The examiner views this as contradictory. It is unclear whether the one or more processors are separate from, or part of, the array, and whether the one or more processors are actually executing the instructions or just sending the instructions to the array for execution by the array. Additionally, it is not clear what is meant by one or more processors coupling caches to the array portions. Does applicant mean that the one or more processors are physically forming a connection between the caches and portions (e.g. via reconfiguration)? Or, does applicant mean that coupling occurs when an operation causes a control word to flow from cache to an array portion? Or, does applicant mean something else that the examiner cannot immediately envision/recognize at this time? Clarification is requested for all of the above and applicant is asked to point to which processors in the specification/drawings correspond to the claimed one or more processors. For purposes of prior art examination, as long as the claimed steps are taught by the prior art, they will be interpreted to be performed by one or more processors.
Claim 22 is rejected for similar reasoning as claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 18, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rousseau et al. (KR 20120140653A), a translation of which is provided herewith.
Referring to claim 1, Rousseau has taught a processor-implemented method for parallel processing comprising:
accessing a two-dimensional array of compute elements (see FIG.1, which shows an array having two dimensions (rows and columns) of compute elements (processing elements (PEs))), wherein each compute element within the array of compute elements is known to a compiler (see p.7, 5th paragraph, and p.8, lines 5-16. A compiler statically schedules instructions to the array since instructions are selected from statically sequenced sequential flows, meaning the compiler is aware of the PEs. Also, “the model…is visible to the instruction centric compiler”) and is coupled to its neighboring compute elements within the array of compute elements (see FIG.1, which shows neighboring PEs coupled to one another through various buses and links (DCLs));
coupling a first control word cache to the array of compute elements, wherein the first control word cache enables loading control words to a first portion of the array of compute elements (see FIG.1, “Instr. Mem 1” (cache), which is connected to PEs in top cluster (defined by the upper dashed boundary) so as to provide instructions (control words) to the PEs of the top cluster);
coupling a second control word cache to the array of compute elements, wherein the second control word cache enables loading control words to a second portion of the array of compute elements (see FIG.1, “Instr. Mem 2” (cache), which is connected to PEs in the bottom cluster (defined by the lower dashed boundary) so as to provide instructions (control words) to the PEs of the bottom cluster);
splitting the control words between the first control word cache and the second control word cache (since there is a split cache, some control words go into “Instr. Mem 1” and some control words go into “Instr. Mem 2”), wherein the splitting is based on constituency of the first portion of the array of compute elements and the second portion of the array of compute elements (the splitting of the control words is based on the PEs in each cluster. The control words destined for the PEs in the top cluster go to “Instr. Mem 1”, and the control words destined for the PEs in the bottom cluster go to “Instr. Mem 2”); and
executing instructions within the array of compute elements, wherein instructions executed within the first portion of the array of compute elements use control words loaded from the first control word cache, and wherein instructions executed within the second portion of the array of compute elements use control words loaded from the second control word cache (as shown in FIG.1, instructions comprising control words from each cache are executed by PEs in the respective cluster).
Referring to claim 2, Rousseau has taught the method of claim 1 further comprising coupling a first control unit between the first control word cache and the first portion of the array of compute elements (at the very least, PEs in the top cluster are coupled to the associated cache via ports/wires/interface, one or more of which is a control unit).
Referring to claim 3, Rousseau has taught the method of claim 2 further comprising coupling a second control unit between the second control word cache and the second portion of the array of compute elements (at the very least, PEs in the bottom cluster are coupled to the associated cache via ports/wires/interface, one or more of which is a control unit).
Referring to claim 4, Rousseau has taught the method of claim 3 wherein the first control unit distributes control word information to the first portion of the array of compute elements (wires/ports/interface for a distribution path through which control word information (instructions or portions thereof) are sent to the respective array portion).
Referring to claim 5, Rousseau has taught the method of claim 4 wherein the second control unit distributes control word information to the second portion of the array of compute elements (wires/ports/interface for a distribution path through which control word information (instructions or portions thereof) are sent to the respective array portion).
Referring to claim 6, Rousseau has taught the method of claim 3 wherein the first control unit and the second control unit operate in lockstep on a cycle-by-cycle basis (from p.12, “Code execution in the lightflow processor is parallel. This parallelism occurs between instructions in an instruction bundle, between instructions on a cluster tile, and between clusters.” Thus, both caches send their control words at the same time (in lockstep) so as to allow for parallel execution. Thus means the ports/wires operate to send data at the same time. Note from p.18, line 4, that a clock is disclosed. Thus, everything is operated on a clock cycle basis over numerous cycles).
Referring to claim 7, Rousseau has taught the method of claim 4 wherein the first control unit and the second control unit operate independently from each other (as the ports/wires/interface of two separate instruction memories are independent/separate, they operate to send data independently).
Referring to claim 18, Rousseau has taught the method of claim 1 wherein the array of compute elements is controlled on a cycle-by-cycle basis by a stream of wide control words generated by the compiler (from the bottom of p.7 to the top of p.9, arithmetic, move, memory access, and branch instructions may execute in parallel. To encode these operations requires more than 1 bit. Thus, the instructions are wide control words. Additionally, control is provided based on clock cycles, as described above).
Claim 21 includes the same steps as claim 1 and is, thus, is mostly rejected for similar reasoning as claim 1. Rousseau has further taught a computer program product embodied in a non-transitory computer readable medium for parallel processing, the computer program product comprising code which causes one or more processors to perform the claimed operations (the one or more processors of the array fetch and execute code, which causes accessing the array (paths are accessed to pass input/outputs, instruction memories/caches in the array are accessed, etc.). Executing the code also causes fetches to occurs from the caches, thereby coupled the caches to the array portions. By loading instructions into the separate caches, the instructions are split across the caches. And, the instructions are executed within the array by the PEs).
Claim 22 is mostly rejected for similar reasoning as claim 21. Rousseau has further taught a computer system for parallel processing comprising: a memory which stores instructions (FIG.1, instruction memories, or main memory (e.g. p.10, 2nd full paragraph), which stores instructions to execute and to be transferred to caches); one or more processors coupled to the memory (FIG.1, PEs), wherein the one or more processors, when executing the instructions which are stored, are configured to perform the claimed steps (again see rejection of claim 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Rousseau in view of Frisson (US 2021/0303207 A1).
Referring to claim 8, Rousseau has taught the method of claim 3 but has not taught wherein the first control unit generates addresses for accessing the first control word cache. However, Rousseau has taught fetching instructions from memory (e.g. p.4, line 11; p.6, lines 7-8, etc.). One implementation to fetch from memory is taught in FIG.1 of Frisson where a memory controller 112 receives generates read addresses to read from memory 116 (e.g. see paragraphs 35-36, 40, etc.). A memory controller is a known component in the art to control read/write/other operations involving memory, thereby freeing a processor from having to perform all tasks a memory controller would normally handle. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rousseau such that the first control unit includes a memory controller that generates addresses for accessing the first control word cache.
Claim 9 is rejected for similar reasoning as claim 8 (each instruction memory would have its own memory controller).
Referring to claim 10, Rousseau has taught the method of claim 3 but has not taught wherein a late load notification signal is driven to both the first control unit and the second control unit at the same time. However, for reasoning given above in the rejections of claims 6 and 8, it would have been obvious to include memory controllers that operate in parallel to fetch instructions in parallel. Further, a late load notification signal may be a signal that causes a load/fetch of an instruction that appears late in the overall program being executed. That is, near the end of executing a given program, the program counter register of Rousseau (p.15, last paragraph) can be said to be providing late load notification signals to the memory controller to read instructions appearing late in the program).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Rousseau.
Referring to claim 12, Rousseau has taught the method of claim 1 but has not taught wherein the first control word cache and the second control word cache are the same size. However, choice of size for an instruction memory is not deemed a patentable distinction, but instead a routine expedient. See MPEP 2144.04, including section (IV)(A). That is, the instruction memories of Rousseau being of the same size or different size has no patentable weight, particularly without a demonstration by applicant of the criticality of the cache size. Here, one of ordinary skill in the art would have recognized the symmetry of the clusters in FIG.1 of Rousseau. They have the same number of PEs, the same interconnections, and the same DCLs. For consistency and simplicity of design, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rousseau such that the first control word cache and the second control word cache are the same size.
Referring to claim 13, Rousseau, as modified, has taught the method of claim 12 wherein the first control word cache and the second control word cache being the same size enables identical cache hit rates and cache misses (from p.7, again note that the instruction memories are instruction caches. Caches experience hits and misses and thus would have a hit rate. Use of “enables” is broad and does not require the claimed caches to actually have the same hit rates, but merely that they can have the same hit rates. Such would be the case in Rousseau. The caches could have the same hit rate and thus they are enabled to have the same hit rate. The caches, also by virtue of being cache, are enabled for experiencing cache misses).
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Rousseau in view of the examiner’s taking of Official Notice.
Referring to claim 14, Rousseau has taught the method of claim 1 but has not taught wherein the first control word cache and the second control word cache each comprise a level-1/level-2 (L1/L2) cache bank. However, Official Notice is taken that a memory hierarchy including L1 and L2 cache banks were well known in the art before applicant’s invention. Memory hierarchy has known advantages in the art including balancing cost, storage capacity, and speed. Here, instead of just a single (L1) cache as shown in FIG.1, a second level of cache (L2 cache) could be implemented to hold instructions that don’t fit into L1 cache, thereby providing a second “fast” level of memory so that slower memory (e.g. main memory) doesn’t always need to be accessed for instructions that don’t fit into L1. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rousseau such that the first control word cache and the second control word cache each comprise a level-1/level-2 (L1/L2) cache bank.
Referring to claim 15, Rousseau, as modified, has taught the method of claim 14 but has not taught coupling a common level-3 (L3) cache to the first control word cache and the second control word cache. However, Official Notice is taken that a memory hierarchy including a shared L3 in addition to L1 and L2 cache banks was well known in the art before applicant’s invention. For similar reasoning set forth in the rejection of claim 14, having an additional level of fast memory can help limit accesses to slower main memory. Sharing a cache reduces cost versus providing multiple L3 caches. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rousseau for coupling a common level-3 (L3) cache to the first control word cache and the second control word cache.
Referring to claim 16, Rousseau has taught the method of claim 1 but has not taught wherein the first control word cache and the second control word cache each store compressed control words. However, Official Notice is taken that storing compressed instructions in cache and decompressing instructions before processing was well known in the art before applicant’s invention. As known, compression reduces the size of the data stored, thereby allowing more data to be cached, which in turn leads to faster access to more instructions. Decompressing them before processing allows the processing logic to be simplified to process one format while allowing any different compression algorithm to be used. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rousseau such that the first control word cache and the second control word cache each store compressed control words.
Claim 17 is rejected for reasoning set forth in the rejection of claim 16.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rousseau in view of Otani et al. (US 6,209,079).
Referring to claim 19, Rousseau has taught the method of claim 18 but has not taught wherein the stream of wide control words comprises variable length control words generated by the compiler. However, Otani has compared and contrasted variable length instructions and fixed length instructions, with variable length instructions resulting in smaller overall code size. They also allow for function expansion (see column 1, line 47, to column 2, line 20). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rousseau such that the stream of wide control words comprises variable length control words generated by the compiler.
Referring to claim 20, Rousseau has taught the method of claim 19 wherein the stream of wide, variable length, control words generated by the compiler provides direct, fine-grained control of the two-dimensional array of compute elements (the wide control words would be sent to the PEs to directly control the array (since this control is at the low instruction level granularity, it is deemed fine-grained control)).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Clarke, 2023/0057903, has taught an array processor with a fully distributed program memory, where each compute element has its own program memory (FIGs.3-4).
Sity, 2022/0164297, has taught multiple array portions, each having a respective cache 230, and what appears to be a shared cache 240 (FIG.2).
Fleming, 2019/0018815, has taught an array divided into domains, with each domain having respective cache banks (FIG.4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183