Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 02/26/2026, in which: claims 1,2 and 4 are amended; and the rejection of the claims 1-8 are traversed. Claims 1-8 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1-8 have been fully considered but are moot in view of the new grounds of rejection.
Claim Objections
Claim 1 objected to because of the following informalities: “…a bit line 6 electrically…” to be corrected to “…a bit line electrically…”Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being anticipated by Okajima et al, US 20220285350, hereafter ‘Okajima’ in view of Atanasov et al, US 20220189957, hereafter ‘Atanasov’.
Regarding claim 1, Okajima discloses : A semiconductor structure, comprising: a substrate including a capacitor(Fig. 67, #2; an upper structure disposed on a top surface of the substrate(upper structure to include #82 and #83); a vertical transistor disposed on the substrate(#1 on #81), in the upper structure(#1 in #82 and #83), and electrically connected to the capacitor(#2 electrically coupled to #1 [0124]); an electrical pad disposed on the vertical transistor(#16).
In this embodiment, Okajima does not teach : wherein the electrical pad has a consistent thickness(Fig. 7, #16 shown to have consistent thickness throughout multiple transistor and is planarized [0331]).
However, in another embodiment Okajima teaches : wherein the electrical pad has a consistent thickness(Fig. 7, #16 shown to have consistent thickness throughout multiple transistor and is planarized [0331]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the electrical pad of figure 37 in one embodiment for the electrical pad of figure 67 because they are known equivalents and it would have yielded the predictable result. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Okajima further teaches : a bit line 6 electrically connected to the electrical pad(Fig. 67, #31 connected to #16); wherein a bottom surface of the bit line is substantially aligned with a top surface of the electrical pad(bottom surface of #31 aligned with top surface of #16); wherein the bit line is disposed on the upper structure at a position that the bottom surface of the bit line is in contact with the top surface of the electrical pad and is in contact with a top surface of the upper structure(#31 disposed on #83 with a bottom surface of #31 contacting both a top surface of #16 and #83); wherein the capacitor is a ring structure(Fig. 6, #2 shown to be a ring structure).
Okajima does not disclose : an upper portion of the capacitor is exposed from a top surface of the substrate.
However, in the same field of endeavor, Atanasov teaches : and an upper portion of the capacitor is exposed from a top surface of the substrate(Fig. 1, #106 may be coplanar with a boundary between two adjacent layers of interlayer dielectric [0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Atanasov to Okajima to have a top surface of a capacitor be exposed at the level of a substrate in memory cells to increase memory density while preserving space for adequate capacitance for enhancing functionality and reducing cost (Atanasov,[0011]).
Regarding claim 2, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 1.
Okajima teaches : wherein the vertical transistor is electrically connected to the capacitor through a conductive material surrounded by a second electrode of the capacitor(Fig. 67, #22 coupled to source/drain of #1[0124] and surrounds #15), wherein a top surface of the conductive material is aligned with the top surface of the substrate(#15 extends to a top surface of #81).
Regarding claim 3, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 2.
Okajima teaches : wherein the second electrode of the capacitor is located outside a vertical projection of the vertical transistor(#22 located outside of #11).
Regarding claim 4, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 1.
Okajima teaches : wherein the upper structure comprises: a bottom insulation layer disposed on the substrate(Fig. 67, #82); a word line disposed on the bottom insulation layer(#12 [0240-0241]); and a top insulation layer disposed on the word line(#83 on #12), wherein the bottom surface of the bit line is in contact with a top surface of the top insulation layer of the upper structure(Bottom surface of #31 on top surface of #83).
Regarding claim 5, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 4.
Okajima teaches : wherein an extension direction of the word line is perpendicular to an extension direction of the bit line(Fig. 66, #BL extending in the y-direction with #WL extending in the x-direction).
Regarding claim 6, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 4.
Okajima teaches : wherein, and the vertical transistor extends through the bottom insulation layer and the word line(Fig. 67, #1 extending through #82 and #12).
Regarding claim 7, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 4.
Okajima teaches : wherein a height of the vertical transistor is greater than a sum of a thickness of the bottom insulation layer and a thickness of the word line(Fig. 67, #1 shown to have a height greater than a sum of thickness of #82 and #12), and the top insulation layer has a consistent thickness(Fig. 67, #83 shown to be a consistent thickness that can be controlled [0322]).
Regarding claim 8, Okajima as modified by Atanasov discloses : The semiconductor structure of Claim 4.
Okajima discloses : wherein a sum of a height of the vertical transistor and the thickness of the electrical pad is substantially equal to a sum of a thickness of the bottom insulation layer, a thickness of the word line and a thickness of the top insulation layer(Fig. 67, #1 is shown to be substantially equal to the thickness of #82, #12, and #83).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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