DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165) in view of Ma et al (US Publication No. 2012/0045880).
Regarding claim 1, Lim discloses a method of manufacturing a semiconductor device, comprising: forming a gate space by removing a sacrificial gate electrode Fig 8;forming a gate dielectric layer Fig 9, 156/256 in the gate space; forming conductive layers on the gate dielectric layer to fully fill the gate space ¶0029-0031 Fig 9;recessing the gate dielectric layer and the conductive layers to form a recessed gate electrode Fig 11 ;and after the recessing, forming a contact metal layer Fig 13, 166/266 on the recessed gate electrode, wherein: the recessed gate electrode does not include a tungsten layer ¶0031, and the contact metal layer includes tungsten ¶0036. Lim discloses all the limitations but silent on reducing the gate sidewall spacer. Whereas Ma discloses forming a gate space by removing a sacrificial gate electrode Fig 4, wherein the gate space is formed by gate sidewall spacers Fig 4, and a liner layer Fig 4, 30 is formed on sidewalls of the gate sidewall spacers Fig 4;reducing a height of the gate sidewall spacers by etching the gate sidewall spacers to expose an upper part of a side surface of the liner layer contacting the gate sidewall spacers Fig 4. Lim and Ma are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method step of Lim and incorporate the teachings of Ma as an alternative method to form the gate electrode and improve active region protection during etching process.
Regarding claim 2, Lim discloses wherein: at least one of the conductive layers has a U-shape cross section Fig 14, and at least one of the conductive layers does not have a U-shape cross section Fig 14, 162C.
Regarding claim 3, Lim discloses wherein the at least one of the conductive layers that does not have a U-shape cross section includes TiN or WCN ¶0031.
Regarding claim 4, Lim discloses wherein the contact metal layer covers a top of the gate dielectric layer Fig 14, 156/256.
Regarding claim 5, Lim discloses wherein an upper surface of the contact metal layer has a convex shape toward the recessed gate electrode ¶0044 Fig 15C. Lim is silent on the shape of the contact metal. It would have been an obvious matter of design choice to modify the shape, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 6, Although Lim discloses the shape of the metal contact. Lim is silent on the specific angle of the slope. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the slope range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Regarding claim 21, Lim discloses method of manufacturing a semiconductor device, comprising: forming a gate space by removing a sacrificial gate electrode Fig 8, the gate space being formed by gate sidewall spacers Fig 9;forming a gate dielectric layer Fig 9, 156/256 in the gate space; forming a first work function adjustment layer Fig 10, 162A/262A on a lower portion of the gate dielectric layer Fig 10, 156/256 ;forming a second work function adjustment layer Fig 10, 162B/262B on the first work function adjustment layer Fig 10, 162A/262A and an upper portion of the gate dielectric layer Fig 10, 156/256 ;forming a body gate electrode layer Fig 11, 162C/262C over the first and second work function adjustment layers to fill the gate space Fig 11;recessing the gate dielectric layer Fig 11, the first and second work function adjustment layers, and the body gate electrode layer to form a recessed gate electrode Fig 11, wherein a top surface of the first work function adjustment layer is higher than a top surface of the second work function adjustment layer Fig 15D; and after the recessing, forming a contact metal layer Fig 15D, 166/266 on the recessed gate electrode Fig 15D. Lim discloses all the limitations but silent on reducing the gate sidewall spacer. Whereas Ma discloses forming a gate space by removing a sacrificial gate electrode Fig 4, wherein the gate space is formed by gate sidewall spacers Fig 4, and a liner layer Fig 4, 30 is formed on sidewalls of the gate sidewall spacers Fig 4;reducing a height of the gate sidewall spacers by etching the gate sidewall spacers to expose an upper part of a side surface of the liner layer contacting the gate sidewall spacers Fig 4. Lim and Ma are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method step of Lim and incorporate the teachings of Ma as an alternative method to form the gate electrode and improve active region protection during etching process.
Regarding claim 22, Lim discloses wherein: the recessed gate electrode does not include a tungsten layer¶0031, and the contact metal layer includes tungsten¶0036.
Regarding claim 23, Lim discloses wherein: each of the first and second work function adjustment layers has a U-shape cross section, and the body gate electrode layer does not have a U-shape cross section Fig 15D.
Regarding claim 24, Lim discloses wherein the at least one of the first and second work function adjustment layers includes TiN or WCN ¶0031.
Regarding claim 25, Lim discloses wherein an upper surface of the contact metal layer has a convex shape toward the recessed gate electrode Fig 15C-15D.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165), Ma et al (US Publication No. 2012/0045880) view of You et al (US Publication No. 2020/0098922).
Regarding claim 7, Lim discloses wherein the contact metal layer is formed by an atomic layer deposition¶0029 .Lim discloses all the limitations but silent on the gas source. Whereas You discloses wherein the contact metal layer is formed by an atomic layer deposition using a fluorine-free W source gas¶0038. Lim and You are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the source gas and incorporate the teachings of You as an alternative source gas known in the art to form Tungsten contact.
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165) and Ma et al (US Publication No. 2012/0045880) in view of Hsueh et al (US Patent No. 9,865,697).
Regarding claim 8, Lim discloses a method of manufacturing a semiconductor device, comprising: forming a gate space by removing a sacrificial gate electrode Fig 8, the gate space being formed by gate sidewall spacers Fig 8;forming a gate dielectric layer Fig 9, 156/256 in the gate space; forming one or more work function adjustment layers Fig 10, 162A/262A on the gate dielectric layer Fig 10, 156/256;removing upper portions of the one or more work function adjustment layers ¶0034; forming a body gate electrode layer Fig 11, 162C/262C over the one or more work function adjustment layers to fill the gate space Fig 10, 162A/262A; recessing the gate dielectric layer, the one or more work function adjustment layers and the body gate electrode layer to form a recessed gate electrode Fig 12; and after the recessing, forming a contact metal layer on the recessed gate electrode Fig 13. Lim discloses all the limitations but silent on the formation of the body gate after the removal of the upper portions of the work function layer. Whereas Hsueh discloses forming one or more work function adjustment layers Fig 1I, 210 on the gate dielectric layer Fig 1I, 180;removing upper portions of the one or more work function adjustment layers Fig 1J-1L;after the removing, forming a body gate electrode layer over the one or more work function adjustment layers to fill the gate space Fig 1N;recessing the gate dielectric layer, the one or more work function adjustment layers and the body gate electrode layer to form a recessed gate electrode Fig 1O. Lim and Hsueh are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the source gas and incorporate the teachings of Hsueh to provide an alternative method that improve the etching/removal process of the metal layers. Lim discloses all the limitations but silent on reducing the gate sidewall spacer. Whereas Ma discloses forming a gate space by removing a sacrificial gate electrode Fig 4, wherein the gate space is formed by gate sidewall spacers Fig 4, and a liner layer Fig 4, 30 is formed on sidewalls of the gate sidewall spacers Fig 4;reducing a height of the gate sidewall spacers by etching the gate sidewall spacers to expose an upper part of a side surface of the liner layer contacting the gate sidewall spacers Fig 4. Lim and Ma are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method step of Lim and incorporate the teachings of Ma as an alternative method to form the gate electrode and improve active region protection during etching process.
Regarding claim 9, Lim discloses wherein: the recessed gate electrode does not include a tungsten layer¶0031, and the contact metal layer includes tungsten¶0036.
Regarding claim 10, Lim discloses wherein: each of the one or more work function adjustment layers has a U-shape cross section Fig 14, and the body gate electrode layer does not have a U-shape cross section Fig 14, 162C.
Regarding claim 11, Lim discloses wherein the at least one of the one or more work function adjustment layers includes TiN or WCN ¶0031.
Regarding claim 12, Lim discloses wherein the contact metal layer covers a top of the gate dielectric layer Fig 13 and 15C-15D.
Regarding claim 13, Lim discloses wherein an upper surface of the contact metal layer has a convex shape toward the recessed gate electrode Fig 15C-15D.
Regarding claim 14, Although Lim discloses the shape of the metal contact. Lim is silent on the specific angle of the slope. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the slope range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165), Ma et al (US Publication No. 2012/0045880) and Hsueh et al (US Patent No. 9,865,697) and in further view of You et al (US Publication No. 2020/0098922).
Regarding claim 15, Lim discloses wherein the contact metal layer is formed by an atomic layer deposition¶0029 .Lim discloses all the limitations but silent on the gas source. Whereas You discloses wherein the contact metal layer is formed by an atomic layer deposition using a fluorine-free W source gas¶0038. Lim and You are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the source gas and incorporate the teachings of You as an alternative source gas known in the art to form Tungsten contact.
Response to Arguments
Applicant’s arguments with respect to claims 1-15, 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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