Prosecution Insights
Last updated: April 19, 2026
Application No. 18/218,482

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jul 05, 2023
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1105 granted / 1312 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
68 currently pending
Career history
1380
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1312 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I in the reply filed on 11/05/2025 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al (US Publication No. 2018/0175165). Regarding claim 1, Lim discloses a method of manufacturing a semiconductor device, comprising: forming a gate space by removing a sacrificial gate electrode Fig 8;forming a gate dielectric layer Fig 9, 156/256 in the gate space; forming conductive layers on the gate dielectric layer to fully fill the gate space ¶0029-0031 Fig 9;recessing the gate dielectric layer and the conductive layers to form a recessed gate electrode Fig 11 ;and after the recessing, forming a contact metal layer Fig 13, 166/266 on the recessed gate electrode, wherein: the recessed gate electrode does not include a tungsten layer ¶0031, and the contact metal layer includes tungsten ¶0036. Regarding claim 2, Lim discloses wherein: at least one of the conductive layers has a U-shape cross section Fig 14, and at least one of the conductive layers does not have a U-shape cross section Fig 14, 162C. Regarding claim 3, Lim discloses wherein the at least one of the conductive layers that does not have a U-shape cross section includes TiN or WCN ¶0031. Regarding claim 4, Lim discloses wherein the contact metal layer covers a top of the gate dielectric layer Fig 14, 156/256. Regarding claim 5, Lim discloses wherein an upper surface of the contact metal layer has a convex shape toward the recessed gate electrode ¶0044 Fig 15C. Regarding claim 21, Lim discloses method of manufacturing a semiconductor device, comprising: forming a gate space by removing a sacrificial gate electrode Fig 8, the gate space being formed by gate sidewall spacers Fig 9;forming a gate dielectric layer Fig 9, 156/256 in the gate space; forming a first work function adjustment layer Fig 10, 162A/262A on a lower portion of the gate dielectric layer Fig 10, 156/256 ;forming a second work function adjustment layer Fig 10, 162B/262B on the first work function adjustment layer Fig 10, 162A/262A and an upper portion of the gate dielectric layer Fig 10, 156/256 ;forming a body gate electrode layer Fig 11, 162C/262C over the first and second work function adjustment layers to fill the gate space Fig 11;recessing the gate dielectric layer Fig 11, the first and second work function adjustment layers, and the body gate electrode layer to form a recessed gate electrode Fig 11, wherein a top surface of the first work function adjustment layer is higher than a top surface of the second work function adjustment layer Fig 15D; and after the recessing, forming a contact metal layer Fig 15D, 166/266 on the recessed gate electrode Fig 15D. Regarding claim 22, Lim discloses wherein: the recessed gate electrode does not include a tungsten layer¶0031, and the contact metal layer includes tungsten¶0036. Regarding claim 23, Lim discloses wherein: each of the first and second work function adjustment layers has a U-shape cross section, and the body gate electrode layer does not have a U-shape cross section Fig 15D. Regarding claim 24, Lim discloses wherein the at least one of the first and second work function adjustment layers includes TiN or WCN ¶0031. Regarding claim 25, Lim discloses wherein an upper surface of the contact metal layer has a convex shape toward the recessed gate electrode Fig 15C-15D. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165). Regarding claim 6, Although Lim discloses the shape of the metal contact. Lim is silent on the specific angle of the slope. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the slope range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165) view of You et al (US Publication No. 2020/0098922). Regarding claim 7, Lim discloses wherein the contact metal layer is formed by an atomic layer deposition¶0029 .Lim discloses all the limitations but silent on the gas source. Whereas You discloses wherein the contact metal layer is formed by an atomic layer deposition using a fluorine-free W source gas¶0038. Lim and You are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the source gas and incorporate the teachings of You as an alternative source gas known in the art to form Tungsten contact. Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165) in view of Hsueh et al (US Patent No. 9,865,697). Regarding claim 8, Lim discloses a method of manufacturing a semiconductor device, comprising: forming a gate space by removing a sacrificial gate electrode Fig 8, the gate space being formed by gate sidewall spacers Fig 8;forming a gate dielectric layer Fig 9, 156/256 in the gate space; forming one or more work function adjustment layers Fig 10, 162A/262A on the gate dielectric layer Fig 10, 156/256;removing upper portions of the one or more work function adjustment layers ¶0034; forming a body gate electrode layer Fig 11, 162C/262C over the one or more work function adjustment layers to fill the gate space Fig 10, 162A/262A; recessing the gate dielectric layer, the one or more work function adjustment layers and the body gate electrode layer to form a recessed gate electrode Fig 12; and after the recessing, forming a contact metal layer on the recessed gate electrode Fig 13. Lim discloses all the limitations but silent on the formation of the body gate after the removal of the upper portions of the work function layer. Whereas Hsueh discloses forming one or more work function adjustment layers Fig 1I, 210 on the gate dielectric layer Fig 1I, 180;removing upper portions of the one or more work function adjustment layers Fig 1J-1L;after the removing, forming a body gate electrode layer over the one or more work function adjustment layers to fill the gate space Fig 1N;recessing the gate dielectric layer, the one or more work function adjustment layers and the body gate electrode layer to form a recessed gate electrode Fig 1O. Lim and Hsueh are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the source gas and incorporate the teachings of Hsueh to provide an alternative method that improve the etching/removal process of the metal layers. Regarding claim 9, Lim discloses wherein: the recessed gate electrode does not include a tungsten layer¶0031, and the contact metal layer includes tungsten¶0036. Regarding claim 10, Lim discloses wherein: each of the one or more work function adjustment layers has a U-shape cross section Fig 14, and the body gate electrode layer does not have a U-shape cross section Fig 14, 162C. Regarding claim 11, Lim discloses wherein the at least one of the one or more work function adjustment layers includes TiN or WCN ¶0031. Regarding claim 12, Lim discloses wherein the contact metal layer covers a top of the gate dielectric layer Fig 13 and 15C-15D. Regarding claim 13, Lim discloses wherein an upper surface of the contact metal layer has a convex shape toward the recessed gate electrode Fig 15C-15D. Regarding claim 14, Although Lim discloses the shape of the metal contact. Lim is silent on the specific angle of the slope. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the slope range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al (US Publication No. 2018/0175165) and Hsueh et al (US Patent No. 9,865,697) and in further view of You et al (US Publication No. 2020/0098922). Regarding claim 15, Lim discloses wherein the contact metal layer is formed by an atomic layer deposition¶0029 .Lim discloses all the limitations but silent on the gas source. Whereas You discloses wherein the contact metal layer is formed by an atomic layer deposition using a fluorine-free W source gas¶0038. Lim and You are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lim because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the source gas and incorporate the teachings of You as an alternative source gas known in the art to form Tungsten contact. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Jul 05, 2023
Application Filed
Nov 18, 2025
Non-Final Rejection — §102, §103
Feb 25, 2026
Examiner Interview Summary
Feb 25, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1312 resolved cases by this examiner. Grant probability derived from career allow rate.

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