Prosecution Insights
Last updated: October 02, 2026
Application No. 18/218,599

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §103
Filed
Jul 06, 2023
Priority
Aug 21, 2017 — TW 106128223 +2 more
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
379 granted / 568 resolved
-1.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
31 currently pending
Career history
600
Total Applications
across all art units

Statute-Specific Performance

§103
55.1%
+15.1% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 568 resolved cases

Office Action

§103
Attorney’s Docket Number: NAUP3120USA3 Filing Date: 7/6/2023 Claimed Priority Dates: 8/5/2020 (US 16/985,242) 9/20/2017 (US 15/710,820) 8/21/2017 (TW 106128223) Inventors: Hsu et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the amendment filed on 5/7/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA (or as subject to pre-AIA ) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The amendment filed on 5/7/2026 in reply to the Office action in paper no. 3, mailed on 3/10/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-11. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2013/0270613) in view of Dyer (US 2008/0237726). Regarding claim 1, Chou (see, e.g., figs. 10) shows most aspects of the instant invention including a method for fabricating a semiconductor device comprising: Forming a gate structure 14 on a substrate 10 Forming a spacer around the gate structure, the spacer comprising an offset spacer 22 adjacent the gate structure and a main spacer 24 adjacent the offset spacer Forming a second contact etch stop layer (CESL2) 42 around the spacer and on and directly contacting the offset spacer 22 and the main spacer 24 Chou, however, fails to teach forming a first contact etch stop layer (CESL1). Dyer, in a similar method to that of Chou, teaches forming a gate structure 100, a spacer 40, and a CESL2 70 directly contacting the spacer (see, e.g., fig. 7). Dyer further teaches the steps of forming a CESL1 68 around and directly contacting the spacer 40 and the substrate 10 (see, e.g., fig. 5), and forming the CESL2 70 on and directly contacting the CESL1 (see, e.g., fig. 7). Chou teaches that the CESL1 increases carrier mobility and the on-current of the device (see, e.g., par.0080/ll.12-21, par.0005 and par.0003/ll.1-4). Accordingly, it would have been obvious at the time of the invention to one of ordinary skill in the art to modify the method of Chou to include the step of Dyer of forming the CESL1, thereby increasing the carrier mobility and on-current of the device. Regarding claim 7, Chou (see, e.g., figs. 7- 9) shows the method further comprising performing a replacement metal gate (RMG) process to transform the gate structure 18 into a metal gate 46 after forming the second CESL 42. Regarding claim 8, Chou (see, e.g., fig 5) shows the method further comprising forming a source/drain region 32 adjacent to two sides of the spacer 22/24 in the substrate before forming the CESL2 42. Dyer (see, e.g., fig. 1) shows forming the source/drain regions 12 adjacent to two sides of the spacer 40 before forming the CESLs. Regarding claim 9, Dyer teaches that the first 68 and second 70 CESLs comprise different materials (see, e.g., par.0057/ll.5-10, par.0063/ll.15-19, an par.0070/ll.1-3). Regarding claim 10, Dyer teaches that the first 68 and second 70 CESLs comprise different dielectric constants (see, e.g., par.0057/ll.5-10, par.0063/ll.15-19, an par.0070/ll.1-3). Regarding claim 11, Dyer (see, e.g., col.6/ll.2-4) teaches that the dielectric constant of the CESL1 68 is lower than that of the CESL2 70 (see, e.g., par.0057/ll.5-10, par.0063/ll.15-19, an par.0070/ll.1-3). Allowable Subject Matter Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments The applicants argue: Dyer fails to show forming a CESL1 around the spacer and on and directly contacting the offset spacer, the main spacer, and the substrate, as recited in claim 1. The examiner responds: The prior art of record teaches these features of the claimed invention, as now recited in claim 1. For example, Chou shows the spacer comprising an offset spacer 38 and a main spacer 24 (see, e.g., fig. 9). Dyer, on the other hand, teaches forming a CESL1 68 around and on and directly contacting the spacer 40 and the substrate 10 (see, e.g., fig. 5). Conclusion This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp July 29, 2026
Read full office action

Prosecution Timeline

Jul 06, 2023
Application Filed
Mar 10, 2026
Non-Final Rejection mailed — §103
May 07, 2026
Response Filed
Jul 31, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751073
VERTICAL THIN FILM TRANSISTOR WITH DUAL GATE ELECTRODES
2y 9m to grant Granted Sep 29, 2026
Patent 12735637
Polymer and Organic Light-Emitting Device Using Same
2y 7m to grant Granted Sep 15, 2026
Patent 12720819
SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED TRANSISTORS
4y 8m to grant Granted Aug 25, 2026
Patent 12709625
ORGANOMETALLIC COMPOUND FOR MASK, LAYER, METHOD FOR PROCESSING ORGANIC SEMICONDUCTOR LAYER, AND METHOD FOR MANUFACTURING ORGANIC SEMICONDUCTOR DEVICE
2y 6m to grant Granted Aug 18, 2026
Patent 12707634
THREE-DIMENSIONAL INTEGRATION STRUCTURE AND METHOD OF FORMING THE SAME
4y 9m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
81%
With Interview (+14.3%)
3y 7m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 568 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month