Prosecution Insights
Last updated: April 19, 2026
Application No. 18/218,599

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Jul 06, 2023
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNITED MICROELECTRONICS CORPORATION
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
3y 8m
To Grant
80%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
358 granted / 546 resolved
-2.4% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
40 currently pending
Career history
586
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§103
Attorney’s Docket Number: NAUP3120USA3 Filing Date: 7/6/2023 Claimed Priority Dates: 8/5/2020 (US 16/985,242) 9/20/2017 (US 15/710,820) 8/21/2017 (TW 106128223) Inventors: Hsu et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the application filed on 7/6/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA (or as subject to pre-AIA ) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2013/0270613) in view of Dyer (US 2008/0237726). Regarding claim 1, Chou (see, e.g., figs. 10) shows most aspects of the instant invention including a method for fabricating a semiconductor device comprising: Forming a gate structure 14 on a substrate 10 Forming a spacer around the gate structure, the spacer comprising an offset spacer 22 adjacent the gate structure and a main spacer 24 adjacent the offset spacer Forming a second contact etch stop layer (CESL2) 42 around the spacer and on and directly contacting the offset spacer 22 and the main spacer 24 Chou, however, fails to show the step of forming a first contact etch stop layer CESL1. Dyer, in a similar method to Chou, also shows the steps of forming a gate structure 100, and the steps of forming a spacer 40, and a second CESL 70 directly contacting the spacer (see, e.g., fig. 7). Dyer further teaches the steps of forming a first CESL 68 around the spacer 40 and directly contacting the substrate 10, and forming the second CESL 70 on and directly contacting the first CESL (see, e.g., figs. 3-7). Chou teaches that his first CESL increases the carrier mobility and the on-current of the device (see, e.g., par.0080/ll.12-21, par.0005 and par.0003/ll.1-4). Accordingly, it would have been obvious at the time of the invention to one of ordinary skill in the art to include the step of forming the first CESL of Dyer in the method of Chou to increase the carrier mobility and on-current of the device. Regarding claim 7, Chou (see, e.g., figs. 7- 9) shows the method further comprising performing a replacement metal gate (RMG) process to transform the gate structure 18 into a metal gate 46 after forming the second CESL 42. Regarding claim 8, Chou (see, e.g., fig 5) shows the method further comprising forming a source/drain region 32 adjacent to two sides of the spacer 22/24 in the substrate before forming the CESL2 42. Dyer (see, e.g., fig. 1) shows forming the source/drain regions 12 adjacent to two sides of the spacer 40 before forming the CESLs. Regarding claim 9, Dyer teaches that the first 68 and second 70 CESLs comprise different materials (see, e.g., par.0057/ll.5-10, par.0063/ll.15-19, an par.0070/ll.1-3). Regarding claim 10, Dyer teaches that the first 68 and second 70 CESLs comprise different dielectric constants (see, e.g., par.0057/ll.5-10, par.0063/ll.15-19, an par.0070/ll.1-3). Regarding claim 11, Dyer (see, e.g., col.6/ll.2-4) teaches that the dielectric constant of the first CESL 68 is lower than that of the second CESL 70 (see, e.g., par.0057/ll.5-10, par.0063/ll.15-19, an par.0070/ll.1-3). Allowable Subject Matter Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Any inquiry of a general nature or relating to the status of this application may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. For more information about the PAIR system, see http://pair-direct.uspto.gov. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. Should you have questions on access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp March 3, 2026
Read full office action

Prosecution Timeline

Jul 06, 2023
Application Filed
Mar 03, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
80%
With Interview (+14.8%)
3y 8m
Median Time to Grant
Low
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allow rate.

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