DETAILED ACTION
This Office Action is in response to Application filed July 6, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group I and Species A drawn to the embodiment shown in Figs. 1 and 3 of current application in the reply filed on January 7, 2026 is acknowledged. The Examiner notes that claims 20, 26 and 33 are directed to a nonelected species shown in Fig. 2 of current application where the fifth barrier 223E is in contact with the active layer 1223 as recited in claims 20, 26 and 33, while the fifth barrier 123E is separated from the active layer 1223 in the elected species shown in Figs. 1 and 3 of current application.
Claim Objections
Claims 16, 21, 22, 27, 29 and 34 are objected to because of the following informalities:
In independent claims 16, 22 and 29, the terms “BEOL” and “FEOL” should be delineated such as “Back End Of Line (BEOL)” and “Front End Of Line (FEOL)”, respectively, because meanings of acronyms can change over time.
In independent claims 16, 22 and 29, and in their dependent claims 17, 21, 23, 27, 30 and 34, the limitations first, second, third and fourth “lateral surface” should be amended, because as recited in claims 16, 22 and 29, the lateral surface of the electrode element extends from the upper surface of the barrier dielectric layer toward/to the lower surface of the barrier dielectric layer, which suggests that the “lateral surface” is actually a “vertical surface” that is laterally disposed with respect to the center of the electrode element.
On line 7 of claim 16, on line 9 of claim 22 and on line 10 of claim 29, “toward to” should be amended, because (a) the preposition “toward” and the preposition “to” may have different meanings, albeit slightly, and (b) therefore, the scope of claims 16, 22 and 29 may be different depending on whether the first lateral surface of the electrode element extends toward the lower surface, or the first lateral surface of the electrode element extends to the lower surface.
On line 3 of claims 21, 27 and 34, “a fourth” should be replaced with “a fourth lateral surface”.
On lines 9-10 of claim 22, the limitation “the first barrier” should be amended, because (a) “a first barrier” recited on line 5 of claim 22 refers to the layer 123’ shown in Figs. 3C_a and 3C_b of current application, while “the first barrier” refers to the patterned layer 123A/123B shown in Figs. 3D_a and 3D_b, (b) therefore, “a first barrier” recited on line 5 is different from “the first barrier” recited on lines 9-10 when a portion of “a first barrier” is removed as recited on line 7, and (c) in this case, the limitation “the first barrier” should be amended to another limitation such as “a remainder of the first barrier” since, when strictly interpreted, the limitation “the first barrier” would be indefinite due to lack of the antecedent basis.
On lines 7-8 of claim 29, the limitation “the upper surface of the barrier dielectric layer” should be amended, because (a) “a barrier dielectric layer” recited on line 2 of claim 29 refers to the layer 121 shown in Figs. 3A_a and 3A_b of current application, while “the barrier dielectric layer” refers to the patterned layer 121 shown in Figs. 3B_a and 3B_b, (b) therefore, “a barrier dielectric layer” recited on line 2 is different from “the barrier dielectric layer” recited on lines 7-8, and (c) in this case, the limitation “the upper surface of the barrier dielectric layer” should be amended to another limitation such as “an upper surface of a patterned barrier dielectric layer through which the through hole is formed” since, when strictly interpreted, the limitation “the upper surface of the barrier dielectric layer” would be indefinite due to lack of the antecedent basis.
On lines 10-11 of claim 29, the limitation “the first barrier” should also be amended, because (a) “a portion of the first barrier” is removed as recited on line 7 of claim 29, and (b) therefore, while “a remaining portion of the first barrier layer” can cover an entirety of the first lateral surface of the electrode element, the first barrier layer cannot exactly cover the entirety of the first lateral surface of the electrode element since “the first barrier” and “the electrode element” do not coexist at the same manufacturing stage.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18, 19, 21, 24, 25, 27, 28, 31, 32, 34 and 35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 18, it is not clear what “a third barrier”, “a third inner wall”, “a fourth barrier” and “a fourth inner wall” recited on lines 3-4 each refers to, because (a) claim 18 depends on claim 16 rather than claim 17 that recites “a second barrier” and “a second inner wall”, (b) however, claim 16 recites only “a first barrier” and “a first inner wall”, and (c) therefore, it is not clear whether there should be an unclaimed second barrier and second inner wall to meet the claim limitations of claim 18, or the third barrier/inner wall should be interpreted as a second barrier/inner wall and the fourth barrier/inner wall should be interpreted as a third barrier/inner wall. Claim 21 depends on claim 18, and therefore, claim 21 is also indefinite.
(2) Regarding claim 19, it is not clear what “a fifth barrier” recited on lines 2-3 refers to, because (a) claim 19 depends on claim 16 rather than claim 17 or claim 18, (b) however, claim 16 recites only “a first barrier” and “a first inner wall”, and (c) therefore, it is not clear whether there should be an unclaimed second, third and fourth barrier to meet the claim limitations of claim 19, or the fifth barrier should be interpreted as a second barrier.
(3) Regarding claim 21, it is not clear what “a third lateral surface” and “a fourth (lateral surface)” recited on lines 2-3 each refers to, because (a) claim 21 depends on claim 18 rather than claim 17, (b) however, claim 18, which in turn depends on claim 16, recites only “a first lateral surface” in claim 16, and (c) therefore, it is not clear whether there should be an unclaimed second lateral surface to meet the claim limitations of claim 21, or the third lateral surface should be interpreted as a second lateral surface.
(4) Regarding claims 24 and 31, claims 24 and 31, which respectively depends on claim 22 and claim 29 rather than claim 23 and claim 30, but reciting “a third barrier” and “a fourth barrier” is indefinite for the same reasons stated above with regard to claim 18 reciting the same limitations. Claim 27 depends on claim 24 and claim 34 depends on claim 31, and therefore, claims 27 and 34 is also indefinite.
(5) Regarding claims 25 and 32, claims 25 and 32, which respectively depends on claim 22 and claim 29 rather than claim 24 and claim 31, but reciting “a fifth barrier” is indefinite for the same reasons stated above with regard to claim 19 reciting the same limitation.
(6) Regarding claims 27 and 34, claims 27 and 34, which respectively depends on claim 24 and claim 31 which in turns respectively depends on claim 22 and claim 39, but reciting “a third lateral surface” and “a fourth (lateral surface)” on lines 2-3 is indefinite for the same reasons stated above with regard to claim 21 reciting the same limitations.
(7) Regarding claims 28 and 35, it is not clear what the limitation “the electrode element is formed on the electrode element” recited on lines 3-4 refers to, because “the electrode element” cannot be “formed on the electrode element” itself.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-18, 21, 29-31, 34 and 35 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Fenouillet-Beranger et al. (US 10,074,802)
Regarding claim 16, Fenouillet-Beranger et al. disclose a manufacturing method for a semiconductor device (Figs. 1A-1K), comprising: forming a barrier dielectric layer (another insulator layer 35 in Fig. 1F) (col. 5, line 61) within a BEOL structure (top portion of Fig. 1F) formed over a FEOL structure (bottom portion of Fig. 1F), because (a) Applicants do not specifically claim what the BEOL and FEOL structure refer to, and what they are constituted of, (b) Applicants’ originally disclosed BEOL and FEOL structures each is a transistor device as disclosed in paragraph [0011] of current application similar to the stack of two transistor devices shown in Fig. 1F of Fenouillet-Beranger et al., and (c) also, Applicants do not specifically claim what the “barrier dielectric layer” refers to, and what it does, and therefore, the another insulator layer 35 can be referred to as “a barrier dielectric layer” since the another insulator layer 35 can function as a barrier against, for example, diffusion or migration of unwanted impurities and propagation of light as well as providing a larger energy barrier in comparison to a semiconductor layer 22 of the transistor T21 since an insulator has an energy band gap larger than an energy band gap of a semiconductor, wherein the barrier dielectric layer (35) has an upper surface (topmost surface of 35) and a lower surface (one of lower surfaces of 35 in contact with T21), because (a) the term “a lower surface” does not necessarily suggest a lowermost or bottommost surface, and (b) one of the two lower surfaces of the another insulator layer 35 in contact with the transistor T21 is thus a lower surface of the another insulator layer 35 or barrier dielectric layer; forming a through hole (one of 44a-44c in Fig. 1H) passing through the barrier dielectric layer; forming a first barrier (patterned layer in Fig. 1K formed from at least one conductor layer 51 in Fig. 1J) (col. 6, lines 31-35) to cover a first inner wall (one inner wall) of the through hole, because (a) Applicants do not specifically claim what the first barrier refers to, what it is formed of, and what its function is, and (b) therefore, the at least one conductor layer 51 can function as a barrier against, for example, diffusion or migration of unwanted impurities especially when the at least one conductor layer 51 is formed of a stack of Ti and TiN as disclosed by Fenouillet-Beranger et al., both of which have been well-known barrier materials in manufacturing semiconductor devices; and forming an electrode element (one of other conductor elements 77a-77c in Fig. 1K) (col. 6, lines 59-61) within the through hole (one of 44a-44c), wherein the electrode element has a first lateral surface extending from the upper surface (topmost surface of 35) toward to the lower surface (one of lower surfaces of 35), and the first barrier (patterned layer in Fig. 1K formed from at least one conductor layer 51 in Fig. 1J) covers an entirety of the first lateral surface of the electrode element.
Regarding claims 17, 18 and 21, Fenouillet-Beranger et al. further comprise forming a second barrier (another portion of patterned 51 in Fig. 1K) to cover a second inner wall (another inner wall of one of 44a-44c) of the through hole (one of 44a-44c); wherein in forming the electrode element (one of 77a-77c) within the through hole, the electrode element further has a second lateral surface (another lateral surface) opposite to the first lateral surface (one lateral surface), and the second lateral surface extends from the upper surface (topmost surface of 35) toward the lower surface (one of lower surfaces of 35 in contact with transistor T21), the second barrier covers an entirety of the second lateral surface of the electrode element (one of 77a-77c) just like the first barrier covers an entirety of the first lateral surface of the electrode element as discussed above with regard to claim 16 (claim 17), further comprising: forming a third barrier (yet another portion of patterned 51 in Fig. 1K into or out of page direction) to cover a third inner wall (yet another inner wall of one of 44a-44c) of the through hole (one of 44a-44c); and forming a fourth barrier (still yet another portion of patterned 51 in Fig. 1K into or out of page direction) to cover a fourth inner wall (still yet another inner wall of one of 44a-44c) of the through hole (claim 18), and in forming the electrode element (one of 77a-77c) within the through hole (one of 44a-44c), the electrode element further has a third lateral surface (yet another of lateral surfaces) and a fourth (still yet another of lateral surfaces) opposite to the third lateral surface, the third lateral surface extends from the upper surface (topmost surface of 35) toward the lower surface (one of lower surfaces of 35), the fourth lateral surface extends from the upper surface toward the lower surface just like the first lateral surface recited in claim 16, the third barrier (yet another portion of patterned 51 in Fig. 1K into or out of page direction) covers an entirety of the third lateral surface of the electrode element, and the fourth barrier (still yet another portion of patterned 51 in Fig. 1K into or out of page direction) covers an entirety of the fourth lateral surface of the electrode element (claim 21).
Please refer to the explanations of the corresponding limitations above.
Regarding claim 29, Fenouillet-Beranger et al. disclose a manufacturing method for a semiconductor device (Figs. 1A-1K), comprising: forming a barrier dielectric layer (35 in Fig. 1F) within a BEOL structure (top portion of Fig. 1F) formed over a FEOL structure (bottom portion of Fig. 1F), wherein the barrier dielectric layer has an upper surface (topmost surface of 35) and a lower surface (one of lower surfaces of 35); forming a through hole (one of 44a-44c in Fig. 1H) passing through the barrier dielectric layer; forming a first barrier (51 or one of Ti and TiN out of stack of Ti and TiN 51 in Fig. 1J) (col. 6, lines 33-35) to cover a first inner wall (one inner wall) of the through hole and the upper surface of the barrier dielectric layer (Fig. 1J); removing a portion of the first barrier which covers the upper surface (topmost surface of 35) of the barrier dielectric layer (step between Fig. 1J and Fig. 1K); and forming an electrode element (one of 77a-77c in Fig. 1K) within the through hole, wherein the electrode element has a first lateral surface (one lateral surface of one of 77a-77c) extending from the upper surface (topmost surface of 35) toward to the lower surface (one of lower surfaces of 53), and the first barrier covers an entirety of the first lateral surface of the electrode element, please also refer to the claim objections of these limitations discussed above.
Regarding claims 30, 31, 34 and 35, Fenouillet-Beranger et al. further comprise forming a second barrier (another portion of 51) to cover a second inner wall (another inner wall) of the through hole (one of 44a-44c); wherein in forming the electrode element (one of 77a-77c) within the through hole, the electrode element further has a second lateral surface (another lateral surface) opposite to the first lateral surface, and the second lateral surface extends from the upper surface toward the lower surface, the second barrier covers an entirety of the second lateral surface of the electrode element (claim 30), further comprising: forming a third barrier (yet another barrier) to cover a third inner wall (yet another inner wall) of the through hole (one of 44a-44c); and forming a fourth barrier (still yet another barrier) to cover a fourth inner wall (still yet another inner wall) of the through hole (claim 31), wherein in forming the electrode element (one of 77a-77c) within the through hole (one of 44a-44c), the electrode element further has a third lateral surface (yet another lateral surface) and a fourth (still yet another lateral surface) opposite to the third lateral surface, the third lateral surface extends from the upper surface toward the lower surface, the fourth lateral surface extends from the upper surface toward the lower surface, the third barrier covers an entirety of the third lateral surface of the electrode element, and the fourth barrier covers an entirety of the fourth lateral surface of the electrode element (claim 34), further comprising: forming an electrode spacer (one of Ti and TiN out of stack of Ti and TiN) (col. 6, lines 33-35) on the first barrier (portion of the other of Ti and TiN out of stack of Ti and TiN); wherein in forming the electrode element (one of 77a-77c) within the through hole (one of 44a-44c), the electrode element is formed on the electrode element, which is indefinite as discussed above under 35 USC 112(b) rejections (claim 35).
Claims 22-24, 27 and 28 and are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Lin et al. (US 2019/0326199)
Regarding claim 22, Lin et al. disclose a manufacturing method for a semiconductor device (Figs. 3-9), comprising: forming a barrier dielectric layer (composite layer disposed above integrated circuits 24 in Fig. 3) ([0015]) within a BEOL structure (top portion of Fig. 3) formed over a FEOL structure (bottom portion including integrated circuits 24 in Fig. 3), because (a) Applicants do not specifically claim what the BEOL and FEOL structure refer to, and what they are constituted of, (b) Applicants’ originally disclosed BEOL structure is a transistor device as disclosed in paragraph [0011] of current application, (c) the top portion of the interconnect structure 26 disposed over the integrated circuits 24 are formed after the integrated circuits 24 are formed, and therefore, the top portion of the interconnect structure 26 can be referred to be a BEOL or Back End Of Line structure just like Applicants’ BEOL structure 120 is formed after Applicants’ FEOL structure 110 is formed as shown in Fig. 1a of current application, and (d) also, Applicants do not specifically claim what the “barrier dielectric layer” refers to, and what it does, and therefore, the composite layer of the plurality of inter-metal dielectrics (IMDs) 34 ([0016]) at and above the metallization layer level M2, and one or more passivation layer(s) 47 ([0017]) disclosed by Lin et al. can be referred to as “a barrier dielectric layer” since the composite layer of the plurality of IMDs 34 and one or more passivation layer(s) 47 can function as a barrier against, for example, diffusion or migration of unwanted impurities and propagation of light, wherein the barrier dielectric layer has an upper surface (topmost surface of 47) and a lower surface (bottom surface of metallization layer M2); forming a through hole (46A in Fig. 4) passing through the barrier dielectric layer; forming a first barrier (insulation layer before it is pattered to form insulation layer 52 in Fig. 5) ([0021]) to cover a first inner wall (one of inner walls of 46A) of the through hole and a bottom of the through hole, because (a) Applicants do not specifically claim what “a first barrier” is formed of, and/or what it does, and (b) therefore, the insulation layer 52 before it is patterned and after it is patterned disclosed by Lin et al. can be referred to as “a first barrier” since the insulation layer 52 can function as a barrier against, for example, diffusion or migration of unwanted impurities and propagation of light; removing a portion of the first barrier which covers the bottom of the through hole ([0021]), because the not-shown insulation layer is patterned, i.e. a portion of the not-shown insulation layer is removed, to expose the top surface of the metal pad 38A as shown in Fig. 5 of Lin et al., while the not-shown insulation layer is not patterned in the opening 44; and forming an electrode element (54 in Fig. 5, or 66 or composite structure of 54 and 66 in Fig. 7) ([0021] and [0023]) within the through hole, wherein the electrode element has a first lateral surface extending from the upper surface (top surface of 47) toward to the lower surface (bottom surface of metallization layer M2), and the first barrier covers an entirety of the first lateral surface of the electrode element.
Regarding claims 23, 24, 27 and 28, Lin et al. further comprise forming a second barrier (another portion of 52) to cover a second inner wall (another inner wall) of the through hole (46A); wherein in forming the electrode element (54, 66 or composite structure of 54 and 66) within the through hole, the electrode element further has a second lateral surface (another lateral surface) opposite to the first lateral surface, and the second lateral surface extends from the upper surface toward the lower surface, the second barrier covers an entirety of the second lateral surface of the electrode element (claim 23), further comprising: forming a third barrier (yet another portion of 52) to cover a third inner wall (yet another inner wall) of the through hole (46A); and forming a fourth barrier (still yet another portion of 52) to cover a fourth inner wall (still yet another inner wall) of the through hole (claim 24), wherein in forming the electrode element (54 or composite structure of 54 and 66) within the through hole (46A), the electrode element further has a third lateral surface (yet another lateral surface) and a fourth (still yet another lateral surface) opposite to the third lateral surface, the third lateral surface extends from the upper surface toward the lower surface, the fourth lateral surface extends from the upper surface toward the lower surface, the third barrier (yet another portion of 52) covers an entirety of the third lateral surface of the electrode element, and the fourth barrier (still yet another portion of 52) covers an entirety of the fourth lateral surface of the electrode element (claim 27), further comprising: forming an electrode spacer (54) on the first barrier (52); wherein in forming the electrode element (66 in Fig. 7) within the through hole (46A), the electrode element is formed on the electrode element, which is indefinite as discussed above under 35 USC 112(b) rejections (claim 28).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsuzaki et al. (US 2020/0203345)
Yamazaki et al. (US 10,923,477)
Yu et al. (US 2015/0235949)
Hong et al. (US 11,527,656)
Chu et al. (US 2024/0347608)
Tsai et al. (US 2024/0234582)
Passlack et al. (US 2020/0135930)
Young et al. (US 2021/0408021)
Chin et al. (US 12,469,745)
Xu et al. (US 2022/0028795)
Yamazaki et al. (US 12,538,523)
Matsuzaki et al. (US 12,349,412)
Murray et al. (US 11,855,226)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J. K./Primary Examiner, Art Unit 2815 March 12, 2026
/JAY C KIM/Primary Examiner, Art Unit 2815