DETAILED ACTION
This Office Action is in response to Amendment filed June 23, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 22 and 29 are objected to because of the following informalities:
In independent claims 22 and 29, the terms “BEOL” and “FEOL” should be delineated such as “Back End Of Line (BEOL)” and “Front End Of Line (FEOL)”, respectively, because meanings of acronyms can change over time.
On lines 8-9 of claim 29, “forming a first barrier material … a patterned barrier dielectric layer through the through hole is formed” should be amended, because this limitation is not grammatical.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16-19, 21-25, 27-32, 34 and 35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
(1) Regarding claims 16, 22 and 29, Applicants did not originally disclose that “the electrode element has a first vertical surface” as recited on lines 9-10 of claim 16, and Applicants did not originally disclose “the first vertical surface of the electrode element” recited on line 12 of claim 12 and on lines 12-13 of claim 29, because (a) Applicants did not use the words “vertical”, “vertically”, “perpendicular”, “orthogonal” or “angle” associated with the claimed configuration or shape of the electrode element, (b) the term “vertical surface” implies that the surface is perpendicular to a top surface of an underlying structure, but the electrode element 1221 shown in Fig. 1 of current application has slanted or inclined surfaces rather than vertical surfaces, (c) rather, the electrode elements 77a-77c shown in Fig. 1K of Fenouillet-Beranger et al. (US 10,074,802) that the Examiner used before in the Non Final Office Action and again in current Office Action have vertical surfaces, and (d) if the Examiner may provide an analogy, Applicants’ usage of the term “vertical surface” is akin to stating that an uphill road is a vertical road. Claims 17-19 and 21 depend on claim 16, claims 23-25, 27 and 28 depend on claim 22, and claims 30-32, 34 and 35 depend on claim 29, and therefore, claims 17-19, 21, 23-25, 27, 28, 30-32, 34 and 35 also fail to comply with the written description requirement.
(2) Regarding claims 17, 23 and 30, Applicants did not originally disclose “a second vertical surface” recited on line 5 of claim 16, and on line 5 of claims 23 and 30 for the same reasons that Applicants did not originally disclose “a first vertical surface” as discussed above. Claims 18, 19 and 21 depend on claim 17, claims 24, 25 and 27 depend on claim 23, and claims 31, 32 and 34 depend on claim 30, and therefore, claims 18, 19, 21, 24, 25, 27, 31, 32 and 34 also fail to comply with the written description requirement.
(3) Regarding claims 21, 27 and 34, Applicants did not originally disclose “a third vertical surface” and “a fourth vertical surface” recited on lines 2-3 of claims 21, 27 and 34 for the same reasons that Applicants did not originally disclose “a first vertical surface” and “a second vertical surface” as discussed above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-25, 27-32, 34 and 35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 22 and 29, it is not clear what “the first vertical surface” and “the electrode element” recited on line 12 of claim 22 and on lines 12-13 of claim 29 each refers to, because (a) Applicants do not claim “a first vertical surface” and “an electrode element” before claiming “the first vertical surface” and “the electrode element”, and (b) therefore, the limitations “the first vertical surface” and “the electrode element” lack the antecedent bases. Claims 23-25, 27 and 28 depend on claim 22, and claims 30-32, 34 and 35 depend on claim 29, and therefore, claims 23-25, 27, 28, 30-32, 34 and 35 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-18, 21, 29-31 and 34 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Fenouillet-Beranger et al. (US 10,074,802)
Regarding claim 16, Fenouillet-Beranger et al. disclose a manufacturing method for a semiconductor device (Figs. 1A-1K), comprising: forming a barrier dielectric layer (another insulator layer 35 in Fig. 1F) (col. 5, line 61) within a Back End Of Line (BEOL) structure (top portion of Fig. 1F) formed over a Front End Of Line (FEOL) structure (bottom portion of Fig. 1F), because (a) Applicants do not specifically claim what the BEOL and FEOL structure refer to, and what they are constituted of, (b) Applicants’ originally disclosed BEOL and FEOL structures each is a transistor device as disclosed in paragraph [0011] of current application similar to the stack of two transistor devices shown in Fig. 1F of Fenouillet-Beranger et al., and (c) also, Applicants do not specifically claim what the “barrier dielectric layer” refers to, and what it does, and therefore, the another insulator layer 35 can be referred to as “a barrier dielectric layer” since the another insulator layer 35 can function as a barrier against, for example, diffusion or migration of unwanted impurities and propagation of light as well as providing a larger energy barrier in comparison to a semiconductor layer 22 of the transistor T21 since an insulator has an energy band gap larger than an energy band gap of a semiconductor, wherein the BEOL structure comprises an active layer (22; semiconductor layer), and the barrier dielectric layer (35) has an upper surface (topmost surface of 35) and a lower surface (one of lower surfaces of 35 in contact with T21), because (a) the term “a lower surface” does not necessarily suggest a lowermost or bottommost surface, and (b) one of the two lower surfaces of the another insulator layer 35 in contact with the transistor T21 is thus a lower surface of the another insulator layer 35 or barrier dielectric layer; forming a through hole (one of 44a-44c in Fig. 1H) passing through the barrier dielectric layer, wherein the through hole extends to or toward the active layer, because Merriam-Webster dictionary defines “to” as being “used as a function word to indicate direction”, which thus does not necessarily have a connotation of an end point or a goal; forming a first barrier (patterned layer in Fig. 1K formed from at least one conductor layer 51 in Fig. 1J) (col. 6, lines 31-35) to cover a first inner wall (one inner wall) of the through hole, because (a) Applicants do not specifically claim what the first barrier refers to, what it is formed of, and what its function is, and (b) therefore, the at least one conductor layer 51 can function as a barrier against, for example, diffusion or migration of unwanted impurities especially when the at least one conductor layer 51 is formed of a stack of Ti and TiN as disclosed by Fenouillet-Beranger et al., both of which have been well-known barrier materials in manufacturing semiconductor devices; and forming an electrode element (one of other conductor elements 77a-77c in Fig. 1K) (col. 6, lines 59-61) within the through hole (one of 44a-44c), wherein the electrode element has a first vertical surface extending from the upper surface (topmost surface of 35) toward to the lower surface (one of lower surfaces of 35), and the first barrier (patterned layer in Fig. 1K formed from at least one conductor layer 51 in Fig. 1J) covers an entirety of the first vertical surface of the electrode element.
Regarding claims 17, 18 and 21, Fenouillet-Beranger et al. further comprise forming a second barrier (another portion of patterned 51 in Fig. 1K) to cover a second inner wall (another inner wall of one of 44a-44c) of the through hole (one of 44a-44c); wherein in forming the electrode element (one of 77a-77c) within the through hole, the electrode element further has a second vertical surface (another vertical surface) opposite to the first vertical surface (one vertical surface), and the second vertical surface extends from the upper surface (topmost surface of 35) toward the lower surface (one of lower surfaces of 35 in contact with transistor T21), the second barrier covers an entirety of the second vertical surface of the electrode element (one of 77a-77c) just like the first barrier covers an entirety of the alleged first vertical surface of the electrode element (claim 17), further comprising: forming a third barrier (yet another portion of patterned 51 in Fig. 1K into or out of page direction) to cover a third inner wall (yet another inner wall of one of 44a-44c) of the through hole (one of 44a-44c); and forming a fourth barrier (still yet another portion of patterned 51 in Fig. 1K into or out of page direction) to cover a fourth inner wall (still yet another inner wall of one of 44a-44c) of the through hole (claim 18), and in forming the electrode element (one of 77a-77c) within the through hole (one of 44a-44c), the electrode element further has a third vertical surface (yet another of vertical surfaces) and a fourth vertical surface (still yet another of vertical surfaces) opposite to the third vertical surface, the third vertical surface extends from the upper surface (topmost surface of 35) toward the lower surface (one of lower surfaces of 35), the fourth vertical surface extends from the upper surface toward the lower surface, the third barrier (yet another portion of patterned 51 in Fig. 1K into or out of page direction) covers an entirety of the third vertical surface of the electrode element, and the fourth barrier (still yet another portion of patterned 51 in Fig. 1K into or out of page direction) covers an entirety of the fourth vertical surface of the electrode element (claim 21).
Please refer to the explanations of the corresponding limitations above.
Regarding claim 29, Fenouillet-Beranger et al. disclose a manufacturing method for a semiconductor device (Figs. 1A-1K), comprising: forming a barrier dielectric layer (35 in Fig. 1F) within a BEOL structure (top portion of Fig. 1F) formed over a FEOL structure (bottom portion of Fig. 1F), wherein the BEOL structure comprises an active layer (22), the barrier dielectric layer has an upper surface (topmost surface of 35) and a lower surface (one of lower surfaces of 35); forming a through hole (one of 44a-44c in Fig. 1H) passing through the barrier dielectric layer, wherein the through hole extends to or toward the active layer; forming a first barrier material (51 or one of Ti and TiN out of stack of Ti and TiN 51 in Fig. 1J) (col. 6, lines 33-35) to cover a first inner wall (one inner wall) of the through hole and an upper surface of a patterned barrier dielectric layer (Fig. 1J) through the through hole is formed; removing a portion of the first barrier material to form a first barrier, wherein the portion of the first barrier covers the upper surface (topmost surface of 35) of the patterned barrier dielectric layer (step between Fig. 1J and Fig. 1K), and a remaining portion of the first barrier material covers an entirety of the first vertical surface of the electrode element (77a, 77b or 77c); and forming an electrode element (one of 77a-77c in Fig. 1K) within the through hole, wherein the electrode element has a first vertical surface (one vertical surface of one of 77a-77c) extending from the upper surface (topmost surface of 35) toward to the lower surface (one of lower surfaces of 53).
Regarding claims 30, 31 and 34, Fenouillet-Beranger et al. further comprise forming a second barrier (another portion of 51) to cover a second inner wall (another inner wall) of the through hole (one of 44a-44c); wherein in forming the electrode element (one of 77a-77c) within the through hole, the electrode element further has a second vertical surface (another vertical surface) opposite to the first vertical surface, and the second vertical surface extends from the upper surface toward the lower surface, the second barrier covers an entirety of the second vertical surface of the electrode element (claim 30), further comprising: forming a third barrier (yet another barrier) to cover a third inner wall (yet another inner wall) of the through hole (one of 44a-44c); and forming a fourth barrier (still yet another barrier) to cover a fourth inner wall (still yet another inner wall) of the through hole (claim 31), wherein in forming the electrode element (one of 77a-77c) within the through hole (one of 44a-44c), the electrode element further has a third vertical surface (yet another vertical surface) and a fourth vertical surface (still yet another vertical surface) opposite to the third vertical surface, the third vertical surface extends from the upper surface toward the lower surface, the fourth vertical surface extends from the upper surface toward the lower surface, the third barrier covers an entirety of the third vertical surface of the electrode element, and the fourth barrier covers an entirety of the fourth vertical surface of the electrode element (claim 34).
Response to Arguments
Applicants’ arguments with respect to claims 16, 22 and 29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wietstruck et al. (US 10,832,953)
Applicants' amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J. K./Primary Examiner, Art Unit 2815 July 30, 2026
/JAY C KIM/Primary Examiner, Art Unit 2815
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