DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 19 December 2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 23 January 2024, 10 September 2025 and 28 January 2026 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4 and 7-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (U.S. Pub. 2022/0302039).
Claim 1: Li et al. discloses a semiconductor device, in Fig. 2E and in paragraphs 23, 31, 33, 39, 41, 51 and 54, comprising:
a substrate (10); and
a wiring structure (126, 142 and 146) comprising:
at least one metal interconnect (126) disposed on the substrate (10);
at least one conductive feature (146) disposed on the metal interconnect (126) and having a head portion (upper portion of 146) and a neck portion (lower portion of 146), wherein the neck portion (lower portion of 146) is between the metal interconnect (126) and the head portion (upper portion of 146), and
at least one diffusion barrier liner (142) to surround the conductive feature (146),
wherein the neck portion (lower portion of 146) has a first critical dimension (width), which gradually decreases at positions of increasing distance from the head portion (upper portion of 146),
wherein the head portion (upper portion of 146) has a second critical dimension (width of upper portion of 146) greater than the first critical dimension (width of lower portion of 146),
wherein an included angle (angle between upper surface of 126 and outer surface of 146) between the neck portion (lower portion of 146) and the metal interconnect (126) is less than 90 degrees.
Claim 4: Li et al. discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E and in paragraph 31, further discloses comprising:
an isolation layer (134) surrounding the head portion (upper portion of 146) of the conductive feature (146); and
a block layer (132) surrounding the neck portion (lower portion of 146) of the conductive feature (146).
Claim 7: Li et al. discloses the semiconductor device of claim 4, and Li et al., in Fig. 2E, further discloses wherein the diffusion barrier liner (142) sandwiched between the conductive feature (146) and the metal interconnect (126), between the conductive feature (146) and the block layer (132), and between the conductive feature (146) and the isolation layer (134).
Claim 8: Li et al. discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E and in paragraphs 32 and 33, further discloses comprising:
an insulative layer (110) surrounding the metal interconnect (126); and
an adhesion liner (122B) interposed between the metal interconnect (126) and the substrate (10) and between the metal interconnect (126) and the insulative layer (110).
Claim 9: Li et al. discloses the semiconductor device of claim 1, and Li et al., in Fig. 2E, further discloses wherein the head portion (upper portion of 146) and the neck portion (lower portion of 146) of the conductive feature (146) are integrally formed.
Claim 10: Li et al. discloses the semiconductor device of claim 1, and Li et al., in paragraphs 33, 52 and 55, further discloses wherein the metal interconnect (126) and the conductive feature (146) have identical conductive materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. as applied to claim 1 above, and further in view of Lin et al. (U.S. Pub. 2015/0318243).
Claim 2: Li et al. discloses the semiconductor device of claim 2.
Li et al. appears not to explicitly disclose wherein the diffusion barrier liner has a first thickness, and smaller values of the included angle correspond to greater values of the first thickness of the diffusion barrier liner.
Lin et al., however, in paragraph 16, discloses the thickness of the diffusion barrier and the included angle are result-effective parameters because the thickness of the diffusion barrier liner (106) and the included angle (sidewall angle of 120) of the conductive feature (120) affects the electrical characteristics of the metal interconnect (104).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to optimize, for example by routine experimentation, the thickness of the diffusion barrier and the included angle of Li et al. in order to have the desire electrical characteristics of the metal interconnect according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Claim 3: Li et al. in view of Lin et al. discloses the semiconductor device of claim 2, and Li et al., in paragraph 39, further discloses the neck portion (lower portion of 146) can have a second thickness (h_v) of 1 nm to 150 nm and the head portion (upper portion of 146) can have a third thickness (h_i) of 2 nm to 150 nm. Therefore, Li et al. in view of Lin et al. discloses the semiconductor device of claim 3, and Li et al. would further disclose wherein the neck portion (lower portion of 146) has a second thickness (h_v), and the head portion (upper portion of 146) has a third thickness (h_i), greater than the second thickness (h_v) (for example, when the second thickness is 1 nm and the third thickness is 2 nm).
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. as applied to claim 4 above, and further in view of Matsuura (U.S. Pub. 2003/0089988).
Claim 5: Li et al. discloses the semiconductor device of claim 4.
Li et al. appears not to explicitly disclose wherein the block layer includes an underlying layer in contact with the metal interconnect and an overlying layer between the underlying layer and the isolation layer.
Matsuura, however, in Fig. 6 and in paragraph 44 and 45, discloses the block layer (8, 9 and 10) includes an underlying layer (8) in contact with the metal interconnect (7) and an overlying layer (10) between the underlying layer (8) and the isolation layer (11).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. with the disclosure of Matsuura to have made the block layer includes an underlying layer in contact with the metal interconnect and an overlying layer between the underlying layer and the isolation layer in order to protect the surrounding elements.
Claim 6: Li et al. in view of Matsuura discloses the semiconductor device of claim 5.
Li et al. in view of Matsuura, as applied to claim 5, appears not to explicitly disclose the underlying layer has a first permittivity, and the overlying layer has a second permittivity greater than the first permittivity.
Matsuura, however, in Fig. 6 and in paragraphs 44 and 45, discloses
the underlying layer (8, which can be SiC, paragraph 46) has a first permittivity (SiC has a relative permittivity of 4.5 to 5.0, paragraph 12), and the overlying layer (10, which can be SiN , paragraph 48) has a second permittivity (SiN has a relative permittivity of 6.5 to 8.0, paragraph 12) greater than the first permittivity.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. in view of Matsuura, as applied to claim 5, with the further disclosure of Matsuura to have made the underlying layer has a first permittivity, and the overlying layer has a second permittivity greater than the first permittivity in order to enhance reliability (paragraph 19 of Matsuura).
Conclusion
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/J.L/
Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815