DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s response filed 06/18/2026 has been fully considered.
The amendment to claim 5 overcomes the previously raised objection.
The amendments to claim 1 and the accompanying arguments with respect to the diffusion barrier liners being in direct contact with the top surface of the semiconductor element and conductive blocks have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al. (US 10,811,595).
The amendments to claim 5 and the accompanying arguments with respect to the arrangement of features relative to the trenches in the dielectric layer have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Barth et al. (US 7,812,424).
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12, in the reply filed on 03/16/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In reference to claim 11, the claim requires “the second diffusion barrier liner disposes … between a sidewall of the second through window and the insulative liner,” in lines 7-9.
This conflicts with the limitation of claim 8, upon which claim 11 depends, of “the insulative liner is formed at and in contact with a sidewall of the second through window,” claim 8, lines 4-5. Therefore, the sequence of layers in the second through window of claim 11 is unclear.
For purposes of examination, claim 11 has been interpreted to mean the second diffusion barrier liner disposes between the second conductive block and the insulative liner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2006/0189137) in view of Lee et al. (US 10,811,595).
In reference to claim 1, Anderson et al. (US 2006/0189137), hereafter “Anderson,” discloses a wiring structure, with reference to Figure 14, comprising
a semiconductor element 12, paragraph 42,
a metallic layer 45a above the semiconductor element, paragraph 54,
at least one first conductive block 32b between the semiconductor element and the metallic layer and having a first critical dimension, and
at least one second conductive block 32a between the semiconductor element and the metallic layer and having a second critical dimension less than the third critical dimension, paragraphs 45 and 50, and
at least one isolation liner 24 enclosing the second conductive feature, paragraphs 47, 48, and 54,
wherein the first conductive block and the second conductive block are surrounded by diffusion barrier liners, 26, respectively,
wherein the diffusion barrier liners are in direct contact with a top surface of the semiconductor element, paragraph 49.
Anderson does not disclose the diffusion barrier liners are in direct contact with the first conductive block and the second conductive block respectively.
Lee et al. (US 10,811,595), hereafter “Lee,” discloses an analogous semiconductor device including teaching diffusion barrier liners, 108 in Figure 1, are in direct contact with the first conductive block and the second conductive block, 110 respectively, col. 5 lines 60 to col. 6 line 10 and col. 6 lines 41-43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the diffusion barrier liners to be in direct contact with the first conductive block and the second conductive block respectively. One would have been motivated to do so in order for the barrier layer to serve as a seed layer for depositing material of the conductive blocks, col. 6 lines 8-10 and 57-64.
In reference to claim 3, Anderson discloses the first conductive block and the second conductive block contact the metallic layer, paragraphs 50 and 54.
In reference to claim 4, Anderson does not disclose a block layer formed on and in contact with the top surface of the semiconductor element wherein the isolation liner is formed between the block layer and one of the diffusion barrier liners and is in contact with the top surface of the semiconductor element.
Lee teaches a block layer, 102 in Figure 1, formed on and in contact with the top surface of the semiconductor element, col. 4 lines 54-55 and col. 5 lines 38-45. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a block layer to be formed on and in contact with the top surface of the semiconductor element. One would have been motivated to do so in order to provide an etch stop layer, col. 5 lines 15-17.
Anderson teaches the isolation liner, 24 in Figure 14, is formed between the opening wall and one of the diffusion barrier liners 26 and is in contact with the top surface of the semiconductor element 12 and Lee teaches the opening wall extending through the block layer 102 in Figure 1. It results naturally from the combination of Anderson and Lee that the isolation liner is formed between the block layer and one of the diffusion barrier liners.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2006/0189137) in view of Lee et al. (US 10,811,595) as applied to claim 1 above and further in view of Allen et al. (US 9,070,751).
In reference to claim 2, Anderson does not disclose wherein a sum of the second critical dimension and two times a thickness of the isolation liner is equal to the first critical dimension.
Allen et al. (US 9,070,751), hereafter “Allen,” discloses a semiconductor device including teaching a first conductive feature 101A in Figure 1, having a first critical dimension 132, a second conductive feature 101B, having a second critical dimension 133 less than the first critical dimension, and at least one isolation liner 121 surrounding the second conductive feature, col. 2 line 60 to col. 3 line 35, wherein a sum of the second critical dimension 133 and two times a thickness of the isolation liner 121 is equal to the first critical dimension 132, Figure 1 and col. 5 lines 7-12 and 30-33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Anderson in view of Allen to form the conductive features of different size by the method of Allen such that a sum of the second critical dimension and two times a thickness of the isolation liner to be equal to the first critical dimension. One would have been motivated to do so in order to form conductors of different sizes with overall smaller feature size as suggested by Allen, col. 1 lines 20-21, to form the larger conductor by omitting the liner from openings of equal width as opposed to a wider opening (as in Anderson).
Claims 5-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Barth et al. (US 7,812,424) in view Allen et al. (US 9,070,751).
In reference to claim 5, Barth et al. (US 7,812,424), hereafter “Barth,” discloses a semiconductor device, with reference to Figure 7G, comprising:
a substrate 43;
a wiring structure, disposed over the substrate, comprising
a first metallic layer M1;
a second metallic layer M2 above the first metallic layer;
at least one first conductive feature V2, between the first and second metallic layers and having a first critical dimension above the first metallic layer;
at least one second conductive feature V2, between the first and second metallic layers and having a second critical dimension above the first metallic layer, col. 9 lines 1-18;
a dielectric layer 41 (of the V2 level) formed and in contact between the first metallic layer M1 and the second metallic layer M2, wherein the dielectric layer has a first trench and a second trench extended through the dielectric layer and formed between the first metallic layer and the second metallic layer, wherein the first trench and the second trench are enclosed by the first metallic layer and the second metallic layer,
an interconnection structure, 110/V1 between the substrate 43 and the wiring structure for connecting the wiring structure to the substrate;
wherein a width of the first trench is equal to a width of the second trench, Figure 1g,
wherein the first conductive feature is enclosed within the first trench at a position that the first conductive feature contacts a sidewall of the first trench, a top surface of the first conductive feature contacts the second metallic layer, and a bottom surface of the first conductive feature contacts the first metallic layer
Barth does not disclose the at least one second conductive feature having a second critical dimension less than the first critical dimension,
at least one isolation liner enclosing the second conductive feature, wherein the isolation liner is formed between a sidewall of the second trench and a sidewall of the second conductive feature,
wherein a sum of the second critical dimension and two times a thickness of the isolation liner is equal to the first critical dimension,
wherein a top surface of the isolation liner is coplanar with a top surface of the second conductive feature, such that the top surface of the isolation liner and the top surface of the second conductive feature contact the second metallic layer, or
wherein a bottom surface of the isolation liner is coplanar with a bottom surface of the second conductive feature, such that the bottom surface of the isolation liner and the bottom surface of the second conductive feature contact the first metallic layer.
Allen discloses a semiconductor device including teaching a first conductive feature 101A in Figure 1, having a first critical dimension 132, a second conductive feature 101B, having a second critical dimension 133 less than the first critical dimension, and at least one isolation liner 121 enclosing the second conductive feature, wherein the isolation liner is formed between a sidewall of the second trench and a sidewall of the second conductive feature, col. 2 line 60 to col. 3 line 35, and a sum of the second critical dimension 133 and two times a thickness of the isolation liner 121 is equal to the first critical dimension 132, and col. 5 lines 7-12 and 30-33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one second conductive feature to have a second critical dimension less than the first critical dimension,
at least one isolation liner to enclose the second conductive feature, wherein the isolation liner is formed between a sidewall of the second trench and a sidewall of the second conductive feature, and
a sum of the second critical dimension and two times a thickness of the isolation liner to be equal to the first critical dimension,
One would have been motivated to do so in order to reduce lateral capacitance and signal coupling, col. 3 lines 36-38.
Allen teaches a top surface of the isolation liner is coplanar with a top surface of the second conductive feature and a bottom surface of the isolation liner is coplanar with a bottom surface of the second conductive feature, Figure 1, and Barth teaches the top surface of the second conductive feature contacts the second metallic layer and the bottom surface of the second conductive feature contacts the first metallic layer, Figure 7g. It results naturally from the combination of Allen and Barth to include the isolation liner of Allen in the second conductive feature of Barth that the top surface of the isolation liner also contacts the second metallic layer, and the bottom surface of the isolation liner also contacts the first metallic layer.
In reference to claim 6, Barth discloses each of the first trench and the second trench has a uniform width, Figure 7g.
In reference to claim 7, Barth discloses the interconnection structure comprises
an insulating layer, 40 in Figure 7f, disposed on the substrate, wherein the insulating layer has a first through window and a second through window extended through the insulating layer, wherein the first through window and the second through window are enclosed by the first metallic layer M1 and the substrate 43,
at least one first conductive block V1 penetrating through the insulating layer and having a third critical dimension,
at least one second conductive block V2 penetrating through the insulating layer,
wherein a width of the first through window is equal to a width of the second through window,
wherein the first conductive block is enclosed within the first through window at a position that a top surface of the first conductive block contacts the first metallic layer M1, while a bottom surface of the first conductive block contacts the substrate 43, and
wherein the second conductive block is enclosed within the second through window at a position that a top surface of the second conductive block contacts the first metallic layer M1, while a bottom surface of the first conductive block contacts the substrate 43.
Barth does not disclose the fourth critical dimension is less than the third critical dimension.
Allen discloses a semiconductor device including teaching a first conductive feature 101A in Figure 1, having a first critical dimension 132, a second conductive feature 101B, having a second critical dimension 133 less than the first critical dimension, col. 2 line 60 to col. 3 line 35 and col. 5 lines 7-12 and 30-33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one second conductive block to have a fourth critical dimension less than the third critical dimension.
One would have been motivated to do so in order to reduce lateral capacitance and signal coupling, col. 3 lines 36-38.
In reference to claim 8, Barth does not disclose at least one insulative liner interposed between the insulating layer and the at least one second conductive block.
Allen discloses a semiconductor device including teaching at least one insulative liner, 121 in Figure 1, interposed between an insulating layer and a second conductive feature 101B, wherein the insulative liner is formed at and in contact with a sidewall of a window, wherein a top surface of the insulative liner is coplanar with the top surface of the second conductive block and wherein a bottom surface of the insulative liner is coplanar with the bottom surface of the second conductive block, col. 2 line 60 to col. 3 line 35, and col. 5 lines 7-12 and 30-33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least one insulative liner to be interposed between an insulating layer and a second conductive feature, wherein the insulative liner is formed at and in contact with a sidewall of the second through window, wherein a top surface of the insulative liner is coplanar with the top surface of the second conductive block and wherein a bottom surface of the insulative liner is coplanar with the bottom surface of the second conductive block,
One would have been motivated to do so in order to reduce lateral capacitance and signal coupling, col. 3 lines 36-38.
Allen teaches a top surface of the isolation liner is coplanar with a top surface of the second conductive feature and a bottom surface of the isolation liner is coplanar with a bottom surface of the second conductive feature, Figure 1, and Barth teaches the top surface of the second conductive block contacts the first metallic layer and the bottom surface of the second conductive feature contacts the substrate, Figure 7g. It results naturally from the combination of Allen and Barth to include the insulative liner of Allen in the second conductive block of Barth that the top surface of the insulative liner also contacts the first metallic layer, and the bottom surface of the insulative liner also contacts the substrate.
In reference to claim 9, Allen discloses wherein a sum of the fourth critical dimension 133 and two times a thickness of the insulative liner 121 is equal to the third critical dimension 132, and col. 5 lines 7-12 and 30-33.
In reference to claim 10, Barth in view of Allen discloses the first conductive block has less resistance than the second conductive block, (an inherent result of the second conductive feature having a smaller cross-sectional area and resistance being inversely proportional to cross-sectional area. Barth discloses the first and second conductive blocks are of the same material and have equal thickness, but in view of Allen, have different cross- sectional areas by the second conductive feature having a width less than the first conductive feature).
In reference to claim 12, Barth discloses the wiring structure is formed over the substrate during back-end-of-line processes, implied by col. 4 lines 23-29 and col. 4 line 60 to col. 5 line 3.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Barth et al. (US 7,812,424) in view Allen et al. (US 9,070,751) as applied to claim 8 above and further in view of Anderson et al. (US 2006/0189137).
In reference to claim 11, Barth discloses a first diffusion barrier liner and a second diffusion barrier liner,
wherein the first diffusion barrier liner is disposed in the first through window and
the second diffusion barrier liner is disposed in the second through window, col. 9 lines 11-17.
Barth is silent regarding the at least one first conductive block and the at least one second conductive blocks are surrounded by the first and second diffusion barrier liners, respectively,
the first diffusion barrier line contacts the substrate and a sidewall of the first through window
the second diffusion barrier liner contacts the substrate and is disposed between a sidewall of the second conductive block and the insulative liner.
Anderson teaches first conductive block 32b and the at least one second conductive blocks 32a are surrounded by first and second diffusion barrier liners 26, respectively,
the first diffusion barrier liner contacts the substrate 12
the second diffusion barrier liner contacts the substrate 12.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one first conductive block and the at least one second conductive blocks to be surrounded by the first and second diffusion barrier liners, respectively,
the first diffusion barrier liner to contact the substrate, and
the second diffusion barrier liner to contact the substrate.
In reference to the first diffusion barrier contacting a sidewall of the first through window, Barth teaches the insulating layer having the first through window as addressed above in reference to claim 7. It results naturally form the combination of Bath and Anderson to include the barrier layer of Anderson in the first window of Barth that the first diffusion barrier contacts a sidewall of the first through window.
In reference to the second diffusion barrier liner being disposed between a sidewall of the second conductive block and the insulative liner, Barth in view of Allen discloses the second conductive block and the insulative liner as addressed above in reference to claim 5. It results naturally from the combination of Barth in view of Allen and Anderson to include the barrier layer of Anderson with the second conductive block of Barth and Allen that the second diffusion barrier liner is disposed between a sidewall of the second conductive block and the insulative liner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims of copending Application No. 17/879,995 in view of Lee et al. (US 10,811,595).
Although the claims at issue are not identical, they are not patentably distinct from each other. The more specific claims of the copending application anticipate the broader claims of this application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
In reference to claim 1, claim 1 of the reference application includes all of the limitations of claim 1 except the first conductive block and the second conductive block are surrounded by diffusion barrier liners respectively.
Lee discloses an analogous semiconductor device including teaching a first conductive block and a second conductive block are surrounded by diffusion barrier liners, 108 in Figure 1, respectively, the diffusion barrier liners, 108 are in direct contact with the top surface of the semiconductor element and are in direct contact with the first conductive block and the second conductive block, 110 respectively, col. 5 lines 60 to col. 6 line 10 and col. 6 lines 41-43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first conductive block and the second conductive block to be surrounded by diffusion barrier liners respectively; wherein the diffusion barrier liners are in direct contact with a top surface of the semiconductor element, and are in direct contact with the first conductive block and the second conductive block respectively. One would have been motivated to do so in order for the barrier layer to serve as a seed layer for depositing material of the conductive blocks, col. 6 lines 8-10 and 57-64.
In reference to claim 2, claim 2 of the reference application includes all of the limitations of claim 2.
In reference to claim 3, claim 4 of the reference application includes all of the limitations of claim 3.
In reference to claim 4, claim 1 includes all of the limitation of claim 4 except the block layer.
Lee teaches a block layer, 102 in Figure 1, formed on and in contact with the top surface of the semiconductor element, col. 4 lines 54-55 and col. 5 lines 38-45. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a block layer to be formed on and in contact with the top surface of the semiconductor element. One would have been motivated to do so in order to provide an etch stop layer, col. 5 lines 15-17.
Claim 1 in view of Lee includes the isolation liner is formed between the opening wall and one of the diffusion barrier liners and is in contact with the top surface of the semiconductor element and Lee teaches the opening wall extending through the block layer 102 in Figure 1. It results naturally from the combination of Claim 1 and Lee that the isolation liner is formed between the block layer and one of the diffusion barrier liners.
Claims 5 and 7-12 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims of copending Application No. 17/879,995 in view of Allen et al. (US 9,070,751).
In reference to claim 5, claim 7 of the reference application includes all of the limitations of claim 5 except a sum of the second critical dimension and two times a thickness of the isolation liner is equal to the first critical dimension.
Allen discloses a semiconductor device including teaching a first conductive feature 101A in Figure 1, having a first critical dimension 132, a second conductive feature 101B, having a second critical dimension 133 less than the first critical dimension, and at least one isolation liner 121 surrounding the second conductive feature, col. 2 line 60 to col. 3 line 35, and a sum of the second critical dimension 133 and two times a thickness of the isolation liner 121 is equal to the first critical dimension 132, and col. 5 lines 7-12 and 30-33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least one isolation liner to enclose the second conductive feature,
wherein a sum of the second critical dimension and two times a thickness of the isolation liner is equal to the first critical dimension.
One would have been motivated to do so in order to reduce lateral capacitance and signal coupling, col. 3 lines 36-38.
In reference to claim 7, claim 11 of the reference application includes all of the limitations of claim 7.
In reference to claim 8, claim 12 of the reference application includes all of the limitations of claim 8.
In reference to claim 9, claim 13 of the reference application includes all of the limitations of claim 9.
In reference to claim 10, claim 7 of the reference application includes all of the limitations of claim 10, (an inherent result of the second conductive feature having a smaller cross-sectional area and resistance being inversely proportional to cross-sectional area).
In reference to claim 11, claim 15 of the reference application includes all of the limitations of claim 11.
In reference to claim 12, claim 16 of the reference application includes all of the limitations of claim 12.
Claim 6 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of copending Application No. 17/879,995 in view of Barth et al. (US 7,812,424).
In reference to claim 6, claim 7 of the reference application includes all of the limitations of claim 6 each of the first trench and the second trench has a uniform width.
In reference to claim 6, Barth discloses each of the first trench and the second trench has a uniform width, Figure 7g. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first trench and the second trench has a uniform width. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one conductor shape for another.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Frohberg et al. (US 2011/0291292), Nakashima (US 2007/0032067), Mikolajick (US 2003/0072195), Allen et al. (US 9,111,935), and Allen et al. (US 9,099,471) disclose related wiring structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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