Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on December 22, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jagueneau et al. (US 2006/0258111).
Regarding claim 21, Jagueneau discloses a method of fabricating a metal-insulator-metal (MIM) capacitor structure, the method comprising:
forming a patterned metallization layer (1a) [Fig. 9];
disposing a dielectric material (2a-2c) on the patterned metallization layer [Fig. 9];
etching one or more deep trenches (3a) through the dielectric material to the patterned metallization layer [Figs. 4 and 9];
depositing a MIM multilayer (4a-5) on the dielectric material and inside the one or more deep trenches formed in the dielectric material, the MIM multilayer including a first conductive layer (4a), a second conductive layer (4c/5), and a dielectric layer (4b) interposed between the first conductive layer and the second conductive layer [Figs. 3 and 9];
fabricating at least one three-dimensional metal-insulator-metal (3D-MIM) capacitor (6) comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches [Fig, 9]; and
fabricating at least one second capacitor (7) including at least one at least one two-dimensional metal-insulator-metal (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material [Fig. 9].
Regarding claim 22, Jagueneau discloses wherein the at least one 2D-MIM capacitor (7) comprises a portion of the MIM multilayer (4a-5) deposited on the dielectric material [Fig. 9].
Regarding claim 23, Jagueneau discloses forming one or more metal traces (1b-1c and Va-Vc) embedded in the dielectric material and that pass between the 2D-MIM (7) and metallization layer (1a) [Fig. 9].
Allowable Subject Matter
Claims 1 and 3-18 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Suo et al. (US 2018/0366401) teaches a 3D MIM capacitor in Figures 4A-4B. And, Voiron et al. (US 2021/0332492) teaches a MIM capacitor in Figure 10.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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