Prosecution Insights
Last updated: April 19, 2026
Application No. 18/219,248

METAL-INSULATOR-METAL CAPACITORS

Non-Final OA §102
Filed
Jul 07, 2023
Examiner
DIAZ, JOSE R
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
799 granted / 922 resolved
+18.7% vs TC avg
Moderate +8% lift
Without
With
+7.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
948
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 922 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Group I in the reply filed on December 22, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jagueneau et al. (US 2006/0258111). Regarding claim 21, Jagueneau discloses a method of fabricating a metal-insulator-metal (MIM) capacitor structure, the method comprising: forming a patterned metallization layer (1a) [Fig. 9]; disposing a dielectric material (2a-2c) on the patterned metallization layer [Fig. 9]; etching one or more deep trenches (3a) through the dielectric material to the patterned metallization layer [Figs. 4 and 9]; depositing a MIM multilayer (4a-5) on the dielectric material and inside the one or more deep trenches formed in the dielectric material, the MIM multilayer including a first conductive layer (4a), a second conductive layer (4c/5), and a dielectric layer (4b) interposed between the first conductive layer and the second conductive layer [Figs. 3 and 9]; fabricating at least one three-dimensional metal-insulator-metal (3D-MIM) capacitor (6) comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches [Fig, 9]; and fabricating at least one second capacitor (7) including at least one at least one two-dimensional metal-insulator-metal (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material [Fig. 9]. Regarding claim 22, Jagueneau discloses wherein the at least one 2D-MIM capacitor (7) comprises a portion of the MIM multilayer (4a-5) deposited on the dielectric material [Fig. 9]. Regarding claim 23, Jagueneau discloses forming one or more metal traces (1b-1c and Va-Vc) embedded in the dielectric material and that pass between the 2D-MIM (7) and metallization layer (1a) [Fig. 9]. Allowable Subject Matter Claims 1 and 3-18 are allowed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Suo et al. (US 2018/0366401) teaches a 3D MIM capacitor in Figures 4A-4B. And, Voiron et al. (US 2021/0332492) teaches a MIM capacitor in Figure 10. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jul 07, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598759
HIGH-DENSITY METAL-INSULATOR-METAL CAPACITOR INTEGRATION WTH NANOSHEET STACK TECHNOLOGY
2y 5m to grant Granted Apr 07, 2026
Patent 12588251
SEMICONDUCTOR MEMORY DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12588226
Integrated Assemblies and Methods Forming Integrated Assemblies
2y 5m to grant Granted Mar 24, 2026
Patent 12578645
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Patent 12581667
MULTISTACK METAL-INSULATOR-METAL (MIM) STRUCTURE USING SPACER FORMATION PROCESS FOR HETEROGENEOUS INTEGRATION WITH DISCRETE CAPACITORS
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 922 resolved cases by this examiner. Grant probability derived from career allow rate.

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