DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16, 21-24 in the reply filed on 09/17/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16, 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duriez(USPGPUB DOCUMENT: 2019/0334027, hereinafter Duriez) in view of Huang (USPGPUB DOCUMENT: 2020/0105634, hereinafter Huang).
Re claim 1 Duriez discloses a method, comprising: forming a first integrated circuit (IC) chip comprising a device region(region of fin), wherein forming the first IC chip comprises: forming a device layer(20) on a substrate[0108], depositing a first dielectric layer(50/45) on a first portion(portion of 50/45), depositing a second dielectric layer(60) on the first dielectric layer(50/45)(Fig 9A) and on a second portion(portion of 20) in the device region(region of fin), and performing a polishing process[0076] on the second dielectric layer(60) to substantially coplanarize a top surface of the second dielectric layer(60) with a top surface of the first dielectric layer(50/45);
Duriez does not discloses forming a first integrated circuit (IC) chip comprising a peripheral region; forming an interconnect structure on the device layer(20),
depositing a first dielectric layer(50/45) on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer(60) on the first dielectric layer(50/45)(Fig 9A) and on a second portion(portion of 20) of the interconnect structure in the device region(region of fin); depositing a second dielectric layer(60) on the first dielectric layer(50/45)(Fig 9A) and on a second portion(portion of 20) of the interconnect structure in the device region(region of fin),
and performing a bonding process on the second dielectric layer(60) to bond a second IC chip to the first IC chip.
Huang discloses forming a first integrated circuit (IC) chip comprising a peripheral region(506)[0017 of Huang]; forming an interconnect structure(520 of Huang) on the device layer(510 of Huang),
depositing a first dielectric layer(50/45) on a first portion of the interconnect structure(520 of Huang) in the peripheral region(506)[0017 of Huang],
and performing a bonding process[0034] on the second dielectric layer[0017] to bond a second IC chip to the first IC chip(flip chip/chip to board)[0017,0034].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sanders to the teachings of Sukumaran in order to minimize packaging defect, circuit failure or reliability concern [0002, Huang]. In doing so, depositing a second dielectric layer(60 of Duriez) on the first dielectric layer(50/45 of Duriez)(Fig 9A) and on a second portion(portion of 20 of Duriez) of the interconnect structure(520 of Huang) in the device region(region of fin of Duriez); depositing a second dielectric layer(60 of Duriez) on the first dielectric layer(50/45 of Duriez)(Fig 9A) and on a second portion(portion of 20 of Duriez) of the interconnect structure(520 of Huang) in the device region(region of fin of Duriez),
Re claim 2 Duriez and Huang disclose the method of claim 1, further comprising masking the second portion(portion of 20) of the interconnect structure prior to depositing the first dielectric layer(50/45).
Re claim 3 Duriez and Huang disclose the method of claim 1, wherein depositing the first dielectric layer(50/45) comprises depositing a nitride layer[0052].
Re claim 4 Duriez and Huang disclose the method of claim 1, wherein depositing the second dielectric layer(60) comprises depositing an oxide layer[0052].
Re claim 5 Duriez and Huang disclose the method of claim 1, wherein performing the polishing process comprises performing chemical mechanical polishing with a polishing chemical that has a higher polishing selectivity for a material of the second dielectric layer(60) than that for a material of the first dielectric layer(50/45).
Re claim 6 Duriez and Huang disclose the method of claim 1, further comprising removing the first dielectric layer(50/45) prior to performing the bonding process.
Re claim 7 Duriez and Huang disclose the method of claim 1, wherein depositing the first dielectric layer(50/45) comprises:depositing a first portion of the first dielectric layer(50/45) on a top surface of the interconnect structure; anddepositing a second portion(portion of 20) of the first dielectric layer(50/45) on a sidewall of the interconnect structure.
Re claim 8 Duriez and Huang disclose the method of claim 1, wherein depositing the first dielectric layer(50/45) comprises depositing a portion of the first dielectric layer(50/45) on sidewalls of the interconnect structure, the device layer(20), and the substrate[0108].
Re claim 9 Duriez and Huang disclose the method of claim 1, wherein depositing the first dielectric layer(50/45) comprises depositing a nitride layer[0052] at a deposition temperature[0086] less than about 400 0C.
Re claim 10 Duriez and Huang disclose the method of claim 1, further comprising depositing a third dielectric layer on a portion of the substrate[0108] in the peripheral region prior to forming the device layer(20) on the substrate[0108].
Re claim 11 Duriez discloses a method, comprising: depositing a first dielectric layer(30) on a first portion of a substrate[0108] of an integrated circuit (IC) chip; forming a fin structure(20/10) on a second portion(portion of 20/10) of the substrate[0108] in a device region(region of 20) of the IC chip; forming a trench(trench formed in Fig 2A) in the fin structure(20/10); depositing a second dielectric layer(28/41) in the trench and on top surfaces of the fin structure(20/10) and the first dielectric layer(30)(see Fig 5A); performing a polishing process[0067] on the second dielectric layer(28/41) to substantially coplanarize a top surface of the second dielectric layer(28/41) with the top surface of the first dielectric layer(30)(see Fig 11A); forming a source/drain (S/D) region on the fin structure(20/10); and depositing an interlayer dielectric (ILD(50)) layer on the S/D region[0062] and on the first dielectric layer(30).
Duriez does not discloses a peripheral region
Huang discloses a peripheral region(506)[0017 of Huang];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sanders to the teachings of Sukumaran in order to minimize packaging defect, circuit failure or reliability concern [0002, Huang].
Re claim 12 Duriez and Huang disclose the method of claim 11, wherein depositing the first dielectric layer(30) comprises:depositing a first portion of the first dielectric layer(30) on a top surface of the substrate[0108]; anddepositing a second portion(portion of 20/10) of the first dielectric layer(30) on a sidewall of the substrate[0108].
Re claim 13 Duriez and Huang disclose the method of claim 11, wherein depositing the first dielectric layer(30) comprises depositing a nitride layer[0065].
Re claim 14 Duriez and Huang disclose the method of claim 11, wherein depositing the second dielectric layer(28/41) comprises depositing an oxide layer[0060].
Re claim 15 Duriez and Huang disclose the method of claim 11, further comprising depositing a third dielectric layer(40) on a portion of the ILD(50) layer in the peripheral region.
Re claim 16 Duriez and Huang disclose the method of claim 15, further comprising forming, on the S/D region[0062], a contact structure(80) with a top surface substantially planarized with a top surface of the third dielectric layer.
Re claim 21 Duriez discloses a method, comprising: forming a device layer(20) on a substrate[0108],; depositing a first dielectric layer(50/45) on a first portion; depositing a second dielectric layer(60) on the first dielectric layer(50/45) and on a second portion(portion of 20) in the device region(region of fin), and performing a polishing process[0076] on the second dielectric layer(60) to substantially coplanarize a top surface of the second dielectric layer(60) with a top surface of the first dielectric layer(50/45).
Duriez does not discloses forming an interconnect structure on the device layer(20); depositing a first dielectric layer(50/45) on a first portion of the interconnect structure in the peripheral region; depositing a second dielectric layer(60) on the first dielectric layer(50/45) and on a second portion(portion of 20) of the interconnect structure in the device region(region of fin)
Huang discloses forming an interconnect structure(520 of Huang) on the device layer(510); depositing a first dielectric layer(112 of Huang) on a first portion of the interconnect structure(520 of Huang) in the peripheral region(506)[0017 of Huang];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sanders to the teachings of Sukumaran in order to minimize packaging defect, circuit failure or reliability concern [0002, Huang]. In doing so, depositing a second dielectric layer(118 of Huang) on the first dielectric layer(112 of Huang) and on a second portion(portion of 520) of the interconnect structure(520 of Huang) in the device region(region of fin)
Re claim 22 Duriez and Huang disclose the method of claim 21, wherein depositing the first dielectric layer(50/45) comprises:depositing a first portion of a nitride layer[0052] on a top surface of the interconnect structure; and depositing a second portion(portion of 20) of the nitride layer[0052] on sidewalls of the interconnect structure, thedevice layer(20), and the substrate[0108].
Re claim 23 Duriez and Huang disclose the method of claim 21, wherein depositing the second dielectric layer(60) comprises depositing an oxide layer[0052].
Re claim 24 Duriez and Huang disclose the method of claim 21, further comprising removing the first dielectric layer(50/45) after performing the polishing process.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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