Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/19/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over KANAMORI (Pub. No.: US 2017/0221921) in view of HWANG (Pub. No.: US 2019/0035798).
Re claim 1, KANAMORI, FIG. 3 teaches a vertical memory structure, comprising: a semiconductor stack, comprising:
a lower semiconductor pattern structure (150, ¶ [0024]) filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate (100);
a contact plug (400), disposed over the lower semiconductor pattern structure,
a filling pattern (280, [0024]) disposed on the lower semiconductor pattern structure (150);
a capping pattern (290) disposed on the filling pattern, wherein the capping pattern is formed between and in contact with the filling pattern (280) and the lower portion of the contact plug (400);
a bit line (420, [0024]) disposed over the lower semiconductor pattern structure (150).
a plurality of gate electrodes (363, 365 and 367, [0024]) surrounding a sidewall of the semiconductor stack; and
a plurality of air gap structures (235, [0066]) disposed at outer sides of the plurality of gate electrode respectively.
KANAMORI fails to teach a contact plug, disposed over the lower semiconductor pattern structure, comprising: a lower portion; a middle portion over the lower portion, wherein a width of the middle portion is less than a width of the lower portion; and an upper portion over the middle portion, wherein the lower portion, the middle portion and the upper portion of the contact plug are made of a same material.
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Moreover, HWANG teaches a contact plug, disposed over the lower semiconductor pattern structure, comprising:
a lower portion (PLG);
a middle portion (SBL) over the lower portion; and
an upper portion ([UofCP], FIG. 4A [as shown above]) over the middle portion, wherein the lower portion, the middle portion and the upper portion of the contact plug are made of a same material.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increased integration density as taught by HWANG, [0002].
Additionally, HWANG fails to teach the width of the middle portion is less than the width of the lower portion, and an upper portion over the middle portion, wherein the lower portion, the middle portion and the upper portion of the contact plug are made of the same material.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Moreover, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include wherein the lower portion, the middle portion and the upper portion of the contact plug are made of a same material because copper can be chosen for the three conductive materials as listed above since it has been held to be within the general skill of a worker in the art to select a known material such as copper on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 2, in the combination, KANAMORI, FIGS. 3-4 teaches the vertical memory structure of claim 1, wherein the plurality of gate electrodes being at a plurality of levels (363, 365 and 367), respectively, so as to be spaced apart from each other in the first direction (vertical);
wherein the semiconductor stack further comprises a charge storage structure (175/1184/245, [0067]) surrounding the filling pattern, wherein the charge storage structure is in contact with the capping pattern (290), wherein the width of the lower portion of the contact plug (horizontal width of 400) is less than a width of the capping pattern (290).
Re claim 3, in the combination, HWANG, FIG. 4A teaches the vertical memory structure of 1, further comprising:
a first insulating interlayer (53/51) disposed over the lower semiconductor pattern structure; and
a second insulating interlayer (60) formed on the first insulating interlayer;
wherein the bit line (BL) is formed on the second insulating interlayer to cover the top surface of the upper portion of the contact plug ([UofCP]/SBL/PLG).
Re claim 4, in the combination, HWANG, FIG. 4A teaches the vertical memory structure of claim 3, wherein a thickness of the first insulating interlayer (51/53) is equal to a height of the lower portion of the contact plug (PLG), wherein a thickness of the second insulating interlayer (60) is equal to a height of the middle portion (SBL) of the contact plug, and wherein a thickness of the bit line (the combine of horizontal thickness of BL) is greater than a height of the upper portion of the contact plug [UofCP];
wherein the height of the lower portion of the contact plug (vertical height of PLG) is greater than the height of the middle portion of the contact plug (SBL).
Re claim 5, in the combination, HWANG, FIG. 4A teaches the vertical memory structure of claim 3, wherein a width of the upper portion [UofCP] is equal to the width of the lower portion (PLG).
Re claim 6, KANAMORI, FIG. 3 teaches the vertical memory structure of claim 3, wherein the lower portion (290), the middle portion (400) and the upper portion (420) are a continuous single structure.
Re claim 7, KANAMORI, FIG. 3 teaches the vertical memory structure of claim 1, wherein each of the plurality of air gap structures comprises:
an air gap (235); and
a liner layer (232) enclosing the air gap.
Re claim 8, in the combination, the vertical memory structure of claim 1, HWANG, FIG. 4A teaches wherein the lower semiconductor pattern structure comprises:
a first undoped semiconductor pattern (LSP, FIG. 5, [0067]);
a doped semiconductor pattern (said doped material of SP1, [0068]) over the first undoped semiconductor pattern; and
a second undoped semiconductor pattern (said undoped material of SP2) over the doped semiconductor pattern.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (Pub. No.: US 2018/0122822) in view of KANAMORI and further in view of HWANG.
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Re claim 1, LEE, FIG. 1 teaches a vertical memory structure, comprising: a semiconductor stack, comprising:
a lower semiconductor pattern structure (200/190/170/180/160) filling a recess on a substrate (100) and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate (100);
a contact plug (380), disposed over the lower semiconductor pattern structure,
a bit line (390, [0041]) disposed over the lower semiconductor pattern structure (251);
a plurality of gate electrodes (343, 345 and 347, [0017]) surrounding a sidewall of the semiconductor stack.
LEE fails to teach a plurality of air gap structures disposed at outer sides of the plurality of gate electrode respectively.
KANAMORI teaches a plurality of air gap structures (235, [0066]) disposed at outer sides of the plurality of gate electrode (363, 365 and 367) respectively.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing the dielectric constant of the insulating stack layers as taught by LEE.
Moreover, LEE/KANAMORI fails to teach a contact plug, disposed over the lower semiconductor pattern structure, comprising: a lower portion; a middle portion over the lower portion, wherein a width of the middle portion is less than a width of the lower portion; and an upper portion over the middle portion, wherein the lower portion, the middle portion and the upper portion of the contact plug are made of a same material.
HWANG teaches a contact plug, disposed over the lower semiconductor pattern structure, comprising:
a lower portion (PLG);
a middle portion (SBL) over the lower portion; and
an upper portion ([UofCP], FIG. 4A [as shown above]) over the middle portion, wherein the lower portion, the middle portion and the upper portion of the contact plug are made of a same material.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increased integration density as taught by HWANG, [0002].
Additionally, HWANG fails to teach the width of the middle portion is less than the width of the lower portion, and an upper portion over the middle portion, wherein the lower portion, the middle portion and the upper portion of the contact plug are made of the same material.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Moreover, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include wherein the lower portion, the middle portion and the upper portion of the contact plug are made of a same material because copper can be chosen for the three conductive materials as listed above since it has been held to be within the general skill of a worker in the art to select a known material such as copper on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 2, in the combination, KANAMORI, FIGS. 3-4 teaches the vertical memory structure of claim 1, wherein the plurality of gate electrodes being at a plurality of levels (363, 365 and 367), respectively, so as to be spaced apart from each other in the first direction (vertical);
wherein the semiconductor stack further comprises a charge storage structure (175/1184/245, [0067]) surrounding the filling pattern, wherein the charge storage structure is in contact with the capping pattern (290), wherein the width of the lower portion of the contact plug (horizontal width of 400) is less than a width of the capping pattern (290).
Re claim 3, in the combination, HWANG, FIG. 4A teaches the vertical memory structure of 1, further comprising:
a first insulating interlayer (53/51) disposed over the lower semiconductor pattern structure; and
a second insulating interlayer (60) formed on the first insulating interlayer;
wherein the bit line (BL) is formed on the second insulating interlayer to cover the top surface of the upper portion of the contact plug ([UofCP]/SBL/PLG).
Re claim 4, in the combination, HWANG, FIG. 4A teaches the vertical memory structure of claim 3, wherein a thickness of the first insulating interlayer (51/53) is equal to a height of the lower portion of the contact plug (PLG), wherein a thickness of the second insulating interlayer (60) is equal to a height of the middle portion (SBL) of the contact plug, and wherein a thickness of the bit line (the combine of horizontal thickness of BL) is greater than a height of the upper portion of the contact plug [UofCP];
wherein the height of the lower portion of the contact plug (vertical height of PLG) is greater than the height of the middle portion of the contact plug (SBL).
Re claim 5, in the combination, HWANG, FIG. 4A teaches the vertical memory structure of claim 3, wherein a width of the upper portion [UofCP] is equal to the width of the lower portion (PLG).
Re claim 6, in the combination, LEE, FIG. 1 teaches the vertical memory structure of claim 3, wherein the lower portion (270), the middle portion (380) and the upper portion (390) are a continuous single structure.
Re claim 7, in the combination KANAMORI, FIG. 3 teaches the vertical memory structure of claim 1, wherein each of the plurality of air gap structures comprises:
an air gap (235); and
a liner layer (232) enclosing the air gap.
Re claim 8, in the combination, LEE, FIG. 1 teaches the vertical memory structure of claim 1, wherein the lower semiconductor pattern structure comprises:
a first undoped semiconductor pattern (160, [0023]);
a doped semiconductor pattern (180) over the first undoped semiconductor pattern; and
a second undoped semiconductor pattern (200) over the doped semiconductor pattern.
Response to Arguments
Applicants’ arguments with respect to claims 1-8 on the remarks filed on 08/19/2026 have been considered but are not persuasive, please see the detail of rejection of listed above.
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2894
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