DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210359142 A1; hereinafter Huang) in view of Guillorn et al. (US 20180254329 A1; hereinafter Guillorn).
Regarding claim 20, FIGS. 23-24 of Huang teach an electronic device comprising: a PMOS (260) comprising a plurality of tempered SiGe channel nanowires (208 of 260 ¶ [0014],[0030]) extending between a p-type source region (source 232 of 260) and a p-type drain region (drain 232 of 260 ¶ [0041]) and a corresponding plurality of oxide layers (242 ¶ [0032]), high-k dielectric layers (244 ¶ [0033]), and conductive material (246 ¶ [0032]) alternatingly stacked with the plurality of strained SiGe channel nanowires (208 of 260); and an NMOS (270) comprising a plurality of Si channel nanowires (208 of 270) extending between an n-type source region (source 2320 of 270) and an n-type drain region (2320 of 270), and a corresponding plurality of oxide layers (243 ¶ [0041]), high-k dielectric layers (244), and conductive material (246) alternatingly stacked with the plurality of Si channel nanowires (208 of 270 ¶ [0023],[0040]-[0041]).
Huang does not teach the PMOS comprising a plurality of compressively stressed SiGe channel nanowires.
FIGS. 13-14 of Guillorn teach an electronic device (semiconductor device ¶ [0001]) comprising: a PFET (e.g. FIGS. 13-14 ¶ [0022]-[0023]) comprising a plurality of compressively stressed SiGe channel nanowires (18 ¶ [0030],[0058]) extending between a p-type source region and a p-type drain region (30 ¶ [0081]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device taught by Huang with the compressively stressed SiGe channel nanowires taught by Guillorn for the purpose of increasing PFET mobility and therefore drive current (¶ [0127]).
Allowable Subject Matter
Claims 1-9 and 11-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a method of forming a semiconductor device, comprising: selectively etching a superlattice structure on a substrate, the superlattice structure extending between a source region and a drain region and comprising a plurality of first layers of a first material and a corresponding plurality of second layers of a second material alternatingly arranged in a plurality of stacked pairs to remove each of the plurality of second layers to form a plurality of voids in the superlattice structure; forming a cladding material around each of the plurality of first layers to form a plurality of nanosheets of the first material with the cladding material around the first material; forming an oxide layer on the cladding material to form a plurality of nanosheets of the first material with the oxide layer and the cladding material around the first material; exposing the semiconductor device to a rapid thermal oxidation process in an environment of one or more of water vapor, oxygen (02), or ozone (03) at a temperature in the range of 700 °C to 1050 °C to dry oxidize the plurality of nanosheets of the first material with the oxide layer and the cladding material around the first material to convert the plurality of nanosheets of the first material with the oxide layer and the cladding material around the first material to have the cladding material surrounded by an oxide of the first material; and removing the oxide of the first material to leave nanosheets of the cladding material.
FIGS. 1-21 & 23-24 of Huang teach a method of forming a semiconductor device (200 ¶ [0016]), comprising: selectively etching a superlattice structure (214C) on a substrate (202, see FIG. 14 ¶ [0027]), the superlattice structure (214C) extending between a source region (source 232) and a drain region (drain 232 ¶ [0024], see FIGS. 12-14) and comprising a plurality of first layers (208) of a first material (e.g. Si) and a corresponding plurality of second layers (206) of a second material (e.g. SiGe) alternatingly arranged in a plurality of stacked pairs (e.g. NMOS & PMOS ¶ [0040], see FIGS. 11 & 13 ¶ [0017]), to remove each of the plurality of second layers (206) to form a plurality of voids (spaces between 2080) in the superlattice structure (214C); forming a cladding material (240, e.g. SiGe) around each of the plurality of first layers (2080) to form a plurality of nanosheets (2080, 240) of the first material (2080, e.g. Si) with the cladding material (240, e.g. SiGe) around the first material (2080, e.g. Si ¶ [0028]); exposing the semiconductor device (200) to a rapid thermal anneal process (300 ¶ [0030]) at a temperature in the range of 700° C to 1050° C (e.g. 600° C to 950° C ¶ [0031]) and subsequently oxidizing the nanosheets (2080, 240) to convert the nanosheets (2080, 240) to have the cladding material (240) surrounded by an oxide of the first material (242, e.g. GeO see FIGS. 16-17 ¶ [0030],[0032],[0042]); and removing the first material (240) to leave nanosheets (2080) of the cladding material (e.g. SiGe ¶ [0037]).
FIGS. 1(a)-(d) of Tezuka et al. (T. Tezuka, N. Sugiyama, S. Takagi, T. Kawakubo; Dislocation-free formation of relaxed SiGe-on-insulator layers. Appl. Phys. Lett. 13 May 2002; 80 (19): 3560–3562.; hereinafter Tezuka) teaches dry oxidizing a mesa island comprising a silicon channel layer and a silicon germanium cladding layer on a substrate (SiO2 on Si substrate) in an environment of pure oxygen (O2)at a temperature of 1050° C (pg. 3560 paragraph 4) to convert the channel to have the material of the cladding layer surrounded by an oxide (SiO2 shown in FIG. 1(c)); and removing the oxide (i.e. oxide of the first material) to leave the channel layer comprising the material of the cladding layer (SiGe, pg. 3560 paragraph 4 recites fabrication process).
However, the prior art fails to teach or reasonably suggest “forming an oxide layer on the cladding material to form a plurality of nanosheets of the first material with the oxide layer and the cladding material around the first material; exposing the semiconductor device to a rapid thermal oxidation process… to dry oxidize the plurality of nanosheets of the first material with the oxide layer and the cladding material” together with all the limitations of claim 1 as claimed. Claims 2-9 and 11-19 are allowable insofar as they depend upon and require all the limitations of claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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