DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/23/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues Tezuka relates to fabrication of dislocation-free strain-relaxed SiGe-on-insulator layers. Thus, Applicant argues, Tezuka does not teach a strained SiGe channel PMOS for a CMOS device.
However, previously relied upon reference Tezuka discloses oxidizing an SiGe cladding layer on an Si layer in an atmosphere of pure oxygen at a temperature of 1050° C to form strained SiGe layers (pg. 3560 paragraph 4, FIGS. 1 & 4). In the disclosure of Tezuka, the formation of strained SiGe layers is considered undesirable since the goal is to form strain-relaxed SGOI layers. Thus, in the disclosure of Tezuka, oxidizing at a temperature of 1200° C is favored. However, within the context of Huang, strained SiGe channels are sought after to provide a desirable threshold voltage (¶ [0014] of Huang).
Thus, the previous obviousness rejection over Huang in view of Tezuka stands. See below.
Regarding claim 20, Applicant argues Huang does not disclose a CMOS device having a PMOS with a strained SiGe channel and an NMOS with a Si channel.
However, paragraphs [0030] and [0031] of Huang explicitly state the anneal process 300 is a germanium drive-in process performed to drive germanium into the channel members 2080. While Huang does not use the word “strained” in reference to the SiGe channels. Paragraph [0014] of Huang states “the silicon channel members in a p-type device region may be ‘tempered’ to provide desirable threshold voltage.” In addition, the process of forming a germanium-containing cladding layer via epitaxy on a silicon layer and annealing to drive germanium into the silicon layer is known to produce strained SiGe layers. For example, Tezuka discloses this process. As previously stated, Tezuka clearly demonstrates annealing Si layers with SiGe cladding at a temperature at or below 1050° C produces strained SiGe.
Thus, the previous anticipation rejection over Huang stands. See below.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210359142 A1; hereinafter Huang).
Regarding claim 20, FIGS. 23-24 of Huang teach an electronic device comprising: a PMOS (260) comprising a plurality of strained SiGe channel nanowires (208 of 260 ¶ [0014],[0030]) extending between a p-type source region (source 232 of 260) and a p-type drain region (drain 232 of 260 ¶ [0041]) and a corresponding plurality of oxide layers (242 ¶ [0032]), high-k dielectric layers (244 ¶ [0033]), and conductive material (246 ¶ [0032]) alternatingly stacked with the plurality of strained SiGe channel nanowires (208 of 260); and an NMOS (270) comprising a plurality of Si channel nanowires (208 of 270) extending between an n-type source region (source 2320 of 270) and an n-type drain region (2320 of 270), and a corresponding plurality of oxide layers (243 ¶ [0041]), high-k dielectric layers (244), and conductive material (246) alternatingly stacked with the plurality of Si channel nanowires (208 of 270 ¶ [0023],[0040]-[0041]).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Tezuka et al. (T. Tezuka, N. Sugiyama, S. Takagi, T. Kawakubo; Dislocation-free formation of relaxed SiGe-on-insulator layers. Appl. Phys. Lett. 13 May 2002; 80 (19): 3560–3562.; hereinafter Tezuka).
Regarding claim 1, FIGS. 1-21 & 23-24 of Huang teach a method of forming a semiconductor device (200 ¶ [0016]), comprising: selectively etching a superlattice structure (214C) on a substrate (202, see FIG. 14 ¶ [0027]), the superlattice structure (214C) extending between a source region (source 232) and a drain region (drain 232 ¶ [0024], see FIGS. 12-14) and comprising a plurality of first layers (208) of a first material (e.g. Si) and a corresponding plurality of second layers (206) of a second material (e.g. SiGe) alternatingly arranged in a plurality of stacked pairs (e.g. NMOS & PMOS ¶ [0040], see FIGS. 11 & 13 ¶ [0017]), to remove each of the plurality of second layers (206) to form a plurality of voids (spaces between 2080) in the superlattice structure (214C); forming a cladding material (240, e.g. SiGe) around each of the plurality of first layers (2080) to form a plurality of nanosheets (2080, 240) of the first material (2080, e.g. Si) with the cladding material (240, e.g. SiGe) around the first material (2080, e.g. Si ¶ [0028]); exposing the semiconductor device (200) to a rapid thermal anneal process (300 ¶ [0030]) at a temperature in the range of 700° C to 1050° C (e.g. 600° C to 950° C ¶ [0031]) and subsequently oxidizing the nanosheets (2080, 240) to convert the nanosheets (2080, 240) to have the cladding material (240) surrounded by an oxide of the first material (242, e.g. GeO see FIGS. 16-17 ¶ [0030],[0032],[0042]); and removing the first material (240) to leave nanosheets (2080) of the cladding material (e.g. SiGe ¶ [0037]).
Huang does not teach a rapid thermal oxidation process in an environment of one or more of water vapor, oxygen (O2), or ozone (O3) to dry oxidize the plurality of nanosheets of the first material with the cladding material around the first material.
FIGS. 1(a)-(d) of Tezuka teaches dry oxidizing a mesa island comprising a silicon channel layer and a silicon germanium cladding layer on a substrate (SiO2 on Si substrate) in an environment of pure oxygen (O2)at a temperature of 1050° C (pg. 3560 paragraph 4) to convert the channel to have the material of the cladding layer surrounded by an oxide (SiO2 shown in FIG. 1(c)); and removing the oxide (i.e. oxide of the first material) to leave the channel layer comprising the material of the cladding layer (SiGe, pg. 3560 paragraph 4 recites fabrication process).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor device taught by Huang with the method of oxidization taught by Tezuka for the purpose of blocking the Ge diffusion out of the channel layer (paragraph 4) and performing the separate annealing and oxidation steps of Huang simultaneously.
Regarding claim 2, Huang teaches the method of claim 1, and Huang further teaches wherein the first material (material of 208/2080) comprises silicon (Si)(¶ [0017]).
Regarding claim 3, Huang as modified teaches the method of claim 1, and Huang further teaches wherein the second material (material of 206) comprises silicon germanium (SiGe)(¶ [0017]).
Regarding claim 4, Huang as modified teaches the method of claim 1, and Huang further teaches wherein the cladding material (240) comprises silicon germanium (SiGe)(¶ [0028]).
Regarding claim 5, Huang as modified teaches the method of claim 4, and Huang further teaches wherein the cladding material (240) is epitaxially grown on the plurality of first layers of the nanosheets (2080 ¶ [0028]).
Regarding claim 7, Huang as modified teaches the method of claim 1.
Huang as modified does not teach removing the oxide of the first material comprises exposing the first material to a dilute HF solution.
However, FIGS. 1 & 8 of Huang teach a selective wet etching process including a hydrogen fluoride etchant (¶ [0023]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor device taught by Huang with the method of selectively etching SiGe oxide for the purpose of selectively removing the oxide material.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Tezuka, and further in view of Colombeau et al. (US 20200152493 A1; hereinafter Colombeau).
Regarding claim 8, Tezuka as modified teaches the method of claim 1.
Huang as modified does not teach further comprising trimming the nanosheets before forming the cladding material to reduce a thickness of the nanosheets from an initial thickness in the range of 6 nm to 8 nm to a reduced thickness in the range of 2 nm to 3 nm.
FIGS. 5-13B of Colombeau teach a method of forming a semiconductor device (500), comprising: selectively etching a superlattice structure (6, 8) on a substrate (2), the superlattice structure comprising a plurality of first layers of a first material (8) and a corresponding plurality of second layers of a second material (6) alternatingly arranged in a plurality of stacked pairs (pairs of 6, 8 ¶ [0055]) to remove each of the second layers (8) to form a plurality of voids (spaces between 8) in the superlattice structure (8 in FIGS. 10A-10B) and a plurality of nanosheets (8) comprising the first layers (8) extending between a source region (source 18) and a drain region (drain 18, see FIGS. 9A-10B); forming a cladding material (24) around each of the plurality of first layers of the nanosheets (8) to form nanosheets having first material with the cladding material around the first material (24 around 8, see FIGS. 12A-12B);
trimming the nanosheets (8 becomes 8’) before forming the cladding material (24) to reduce a thickness of the nanosheets from an initial thickness in the range of 6 nm to 8 nm (e.g. 5 nm to 10 nm ¶ [0055]) to a reduced thickness in the range of 2 nm to 3 nm (e.g. 2 nm to 3 nm ¶ [0068], see FIGS. 10A-11B).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor device taught by Huang with the method of trimming the nanosheets taught by Colombeau for the purpose of improving the threshold voltage, drive current, and reliability of the device (¶ [0019]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Tezuka and Colombeau, and further in view of Wang et al. (US 20210343858 A1; hereinafter Wang).
Regarding claim 9, Huang as modified teaches the method of claim 8.
Huang as modified does not teach wherein nanosheets closer to the substrate have a greater reduced thickness than nanosheets further from the substrate.
FIGS. 14-21 of Wang teach a method of forming a semiconductor device, comprising: a trimming process (270) which reduces the thickness of nanosheets (220) of a superlattice structure (212b-212c) on a substrate (208 ¶ [0052], see FIG. 18),
wherein nanosheets closer to the substrate (220 closer to 208) have a greater reduced thickness than nanosheets further from the substrate (220 furthest from 208 ¶ [0052], see FIG. 18).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor device taught by Huang with the nanosheet trimming process taught by Wang for the purpose of tuning the threshold voltage (¶ [0013],[0052]).
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Tezuka, and further in view of Cheng et al. (US 20210249517 A1; hereinafter Cheng).
Regarding claim 15, Huang as modified teaches the method of claim 1.
Huang as modified does not teach further comprising forming a silicon cap on the nanosheets of the cladding material by epitaxial growth or by chemical vapor deposition.
FIG. 11K of Cheng teaches forming a gate work function layer (130A-D) including a silicon cap (1116) on a plurality of nanosheets (122 ¶ [0025],[0037],[0092]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor device taught by Huang with the formation of the gate work function layer taught by Cheng for the purpose of preventing substantial diffusion of metals to underlying layers (¶ [0037]).
Huang as modified does not explicitly teach forming the silicon cap by epitaxial growth or chemical vapor deposition.
However, Huang teaches forming silicon layers (208) by epitaxial growth or by chemical vapor deposition (¶ [0017]).
Regarding claim 16, Huang as modified teaches the method of claim 15, and Cheng further teaches wherein the silicon cap (1116) has a thickness in the range of 2 Å to 20 Å (e.g. 10 Å to 13 Å ¶ [0092]).
Regarding claim 17, Huang as modified teaches the method of claim 15, and FIG. 18 of Huang further teaches further comprising forming a high-k metal gate (244, 246) in contact with the nanosheets of cladding material (2080 ¶ [0033],[0034]).
Regarding claim 18, Huang as modified teaches the method of claim 1.
Huang as modified does not teach further comprising forming the superlattice structure on a top surface of a substrate, each of the first layers and second layers having thickness independently in the range of 3 nm to 20 nm.
FIGS. 2-3C of Cheng teach forming a superlattice structure (108B) on a top surface of a substrate (106), each of a plurality of first layers (122) and second layers (320) having a thickness (320t and 122t) independently in the range of 3 nm to 20 nm (e.g. 6 nm to 10 nm ¶ [0049]-[0050]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor device taught by Huang with the thicknesses of the first and second layers taught by Cheng since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thickness of the channel layers and sacrificial layers determines the resulting device dimensions making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 19, Huang as modified teaches the method of claim 18, and FIGS. 1 and 9 of Huang further teach further comprising forming the source region (source 232) adjacent a first end of the superlattice structure (first end of 214C) and the drain region (drain 232) adjacent a second opposing end of the superlattice structure (second end of 214C ¶ [0024]).
Allowable Subject Matter
Claims 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 recites the method of claim 1, further comprising forming an oxide on the cladding material before dry oxidation.
Huang in view of Tezuka teaches the method of claim 1.
However, the prior art fails to teach or reasonably suggest “further comprising forming an oxide on the cladding material before dry oxidation” together with all the limitations of claims 1 and 10 as claimed. Claims 11-14 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 1 and 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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