Attorney Docket Number: LOUIS-60570DIV
Filing Date: 7/11/2023
Claimed Foreign Priority Date: 11/12/2020 (TW109139525)
Inventors: Chen et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the RCE amendments filed on 2/27/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/27/2026 has been entered.
Amendment Status
The RCE submission filed on 1/23/2026 as an amendment in reply to the Office action mailed on 1/06/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 12-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-20 are rejected under 35 U.S.C. 103as being unpatentable over Lin (US 20210193577 A1) in view of Yu (US 20200105675 A1).
Regarding claim 12, Lin (see, e.g., fig. 3) shows most aspects of the instant invention, including a method of manufacturing an electronic package (e.g., package structure 100b) comprising:
Providing an electronic body (e.g., bridge die 36) having a first side (e.g., bottom surface adjacent to under filling portion 40a) and a second side (e.g., top surface adjacent to polymer layer PM1) opposite to each other, and including a base (e.g., substrate 33 (see fig. 1H)) and a circuit portion (e.g., interconnect layer 34 (see fig. 1G)) formed on the base (e.g., substrate 33 (see fig. 1H)), wherein the second side (e.g., top surface adjacent to polymer layer PM1) is defined by the base (e.g., substrate 33 (see fig. 1H)), and the first side is defined by the circuit portion (e.g., interconnect layer 34 (see fig. 1G)), and the base (e.g., substrate 33 (see fig. 1H)) includes a plurality of conductive vias (e.g., through substrate vias 60) electrically connected to the circuit portion (e.g., interconnect layer 34 (see fig. 1G)) and exposed from the second side (e.g., top surface adjacent to polymer layer PM1);
Forming a plurality of first conductors (e.g., connectors 31) and second conductors (e.g., RDL1 + paragraph 54 “The redistribution layer RDL1 further includes vias landing on the TSVs 60”) on the first side (e.g., bottom surface adjacent to under filling portion 40a) and second side (e.g., top surface adjacent to polymer layer PM1) of the electronic body (e.g., bridge die 36), respectively, wherein the first conductors (e.g., connectors 31) are electrically connected to the circuit portion (e.g., interconnect layer 34 (see fig. 1G)), and the second conductors (e.g., RDL1 + paragraph 54 “The redistribution layer RDL1 further includes vias landing on the TSVs 60”) are electrically connected with the conductive vias (see, e.g., paragraph 54 “The redistribution layer RDL1 further includes vias landing on the TSVs 60”);
Forming a bonding layer (e.g., under filling portion 40a) and an insulating layer (e.g., PM1 + PM2) on the first side (e.g., bottom surface adjacent to under filling portion 40a) and the second side (e.g., top surface adjacent to polymer layer PM1) of the electronic body (e.g., bridge die 36), respectively, wherein the first conductors (e.g., connectors 31) are covered by the bonding layer (e.g., under filling portion 40a), and the second conductors (e.g., RDL1 + paragraph 54 “The redistribution layer RDL1 further includes vias landing on the TSVs 60”) are covered by the insulating layers (e.g., PM1 + PM2) to form an electronic structure (e.g., structure comprising aforementioned bonding layer + insulating layer + first and second conductors);
Disposing the electronic structure (e.g., structure comprising aforementioned bonding layer + insulating layer + first and second conductors…) on a carrier (e.g., carrier 10, see fig. 1I) with the bonding layer (e.g., under filling portion 40a) thereof; a plurality of conductive pillars (e.g., conductive posts 30) being formed on the carrier (e.g., carrier 10);
Forming an encapsulation layer (e.g., encapsulant 40) on the carrier (e.g., carrier 10) to cover the electronic structure (e.g., structure comprising aforementioned bonding layer + insulating layer + first and second conductors) and the conductive pillars (e.g., conductive posts 30), wherein the encapsulation layer (e.g., encapsulant 40) has a first surface (e.g., bottom surface of encapsulant 40) and a second surface (e.g., top surface of encapsulant 40) opposite to each other, and the encapsulation layer (e.g., encapsulant 40) is bonded to the carrier (e.g., carrier 10) at the first surface (e.g., bottom surface of encapsulant 40, through circuit structure in encapsulant 19) thereof; and
Removing the carrier (e.g., carrier 10 + see fig. 3, note that carrier 10 from fig. 1I was removed);
Lin (see, e.g., fig. 3), however, fails to show the encapsulation layer covers side surfaces of the insulating layer.
Yu (see, e.g., fig. 5), in a similar device to Lin, teaches an encapsulation layer (e.g., insulating encapsulation 140) covering side surfaces (e.g., note that the encapsulation 140 surrounds the protection layer 130 portion) of an insulating layer (e.g., dielectric layers 152 + protection layers 130e + paragraph 26 “…the protection layer 130e may be made of…silicon oxide, silicon nitride…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the extended insulation profile of Yu between the vias of Lin (thus some of the side surfaces of the profile are covered by the encapsulation layer), in order to provide a protection/dielectric profile surrounding the vias, preventing potential electrical shorting within the device.
Regarding claim 13, Lin (see, e.g., fig. 3) shows the base (e.g., substrate 33 (see fig. 1H)) of the electronic body (e.g., bridge die 36) is a silicon material (see, e.g., paragraph 30 “the substrate 33 may be a semiconductor substrate…the semiconductor substrate is, for example, a doped silicon substrate, an undoped silicon substrate…”).
Regarding claim 14, Lin (see, e.g., fig. 3) shows the first conductors are (e.g., connectors 31) are metal pillars or solder materials (see, e.g., paragraph 29 “…a plurality of connectors 31, such as solder bumps, gold bumps, copper bumps, or the like or any other suitable metallic balls”).
Regarding claim 15, Lin (see, e.g., fig. 1E to fig. 1H) shows before disposing the electronic structure (e.g., structure comprising aforementioned bonding layer + insulating layer + first and second conductors) on the carrier (e.g., carrier 10), forming auxiliary conductors (e.g., pads 35) on the first conductors (e.g., connectors 31 + note that auxiliary conductors were formed in fig. 1F, with the full electronic structure not being formed until 1I) with the auxiliary conductors (e.g., pads 35) being covered (see, e.g., fig. 1H for bonding layer formation) by the bonding layer (e.g., under filling portion 40a).
Regarding claim 16, Lin (see, e.g., fig. 1G) shows before disposing the electronic structure (e.g., structure comprising aforementioned bonding layer + insulating layer + first and second conductors) on the carrier (e.g., carrier 10) exposing the first conductors (e.g., connectors 31) from the bonding layer (e.g., under filling portion 40a + note that first conductors in fig. 1G are openly exposed, free of the bonding layer (which is deposited in the subsequent steps)).
Regarding claim 17, Lin (see, e.g., fig. 3) shows the second surface (e.g., top surface of encapsulant 40) of the encapsulation layer (e.g., encapsulation 40) is flush with ends of the conductive pillars, the insulating layer (e.g., see PM1 spread across the second surface of the encapsulation layer) or the second conductors (e.g., RDL1)
Regarding claim 18, Lin (see, e.g., fig. 3) shows ends of the conductive pillars (e.g., conductive posts 30), the insulating layer (e.g., PM1 + PM2) or the second conductors (e.g., RDL1) are exposed from the second surface (e.g., top surface of encapsulant 40) of the encapsulation layer (e.g., encapsulation 40).
Regarding claim 19, Lin (see, e.g., fig. 3) shows forming a circuit structure (e.g., substrate 13 + connectors 16 and plurality of pads 14) on the first surface (e.g., bottom surface of encapsulant 40) of the encapsulation layer (e.g., encapsulant 40) to electrically connect the circuit structure (e.g., substrate 13 + connectors 16 + plurality of pads 14) with the electronic structure (e.g., structure comprising aforementioned bonding layer + insulating layer + first and second conductors) and the plurality of conductive pillars (e.g., conductive posts 30).
Lin (see, e.g., fig. 3) in view of Yu, however, fails to explicitly teach that this process is done after removing the carrier.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify the order of steps when starting the method using a slightly different arrangement containing substantially similar parts. Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959) (Prior art reference disclosing a process of making a laminated sheet wherein a base sheet is first coated with a metallic film and thereafter impregnated with a thermosetting material was held to render prima facie obvious claims directed to a process of making a laminated sheet by reversing the order of the prior art process steps.). See also In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930) (Selection of any order of mixing ingredients is prima facie obvious.). Therefore, it would have been obvious to include the original electronic structure of Lin directly on the carrier, before removing said carrier and connecting the electronic structure with a circuit structure, as opposed to starting the process with a circuit structure, attaching an electronic structure, and then finally removing the carrier.
Regarding claim 20, Lin (see, e.g., fig. 3) shows the first conductors (e.g., connectors 31) are electrically connected with the circuit structure (e.g., substrate 13 + connectors 16 + plurality of pads 14) through conductive bumps (e.g., conductive pads 27).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS WILSON MCCOY whose telephone number is (571)272-0282. The examiner can normally be reached 8:30-6:00 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814