DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 112 3
A. Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. 3
IV. Claim Rejections - 35 USC § 103 3
A. Claims 1, 2, 8-11 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over CN 112820713 A (“Chen-713”). 4
D. Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-713, as applied to claims 1 and 2, above, and further in view of US 2021/0210427 (“Kang”) and as evidenced by US 5,257,000 (“Billings”) only for claim 5. 9
C. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen-713, as applied to claim 1, above, and further in view of US 2012/0229990 (“Adachi”). 11
D. Claims 3-6 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-713, as applied to claims 1 and 2, above, and further in view of CN 112164677 A as evidenced by US 2022/0068760 (collectively “Chen-760”). 12
V. Pertinent Prior Art 16
Conclusion 16
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of species group II in the reply filed on 11/17/2025 is acknowledged. Claims 1-11 and 13-20 are either generic or read on the elected species.
III. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 9 reads,
9. The manufacturing method according to claim 1, wherein the adhesive layer in step (b) comprises an adhesive tape.
There is insufficient antecedent basis for “step (b)” in the claim.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 2, 8-11 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over CN 112820713 A (“Chen-713”).
Although Chen-713 shares several common inventors and a common assignee with the Instant Application, Chen-713 published more than one year before the filing of the Instant Application and is therefore available as prior art under 35 USC 102(a)(1), and there exist no exceptions under 35 USC 102(b) to disqualify Chen-713 as prior art.
All citations to Chen-713 are from the attached machine-language translation.
With regard to claim 1, Chen-713 discloses, generally in Figs. 2(a)-2(l),
1. A method for manufacturing a device embedded packaging structure, the method comprising:
[1a] laminating a first dielectric material on at least one face of a copper foil 1011 [p. 9, lines 38-41] to form a first dielectric layer [not shown; see explanation below], and
[1b] forming a first feature pattern in the first dielectric layer to expose the copper foil 1011 [not shown but corresponds to the pattern shown in Fig. 2(a); see explanation below];
[2] etching an exposed copper foil 1011 to form a device opening frame 1013 and a via post opening frame 1012 so as to obtain a metal frame [Fig. 2(b); paragraph bridging pp. 9-10];
[3] applying an adhesive layer 102 on a bottom surface of the metal frame 101, and mounting a device 103 on the adhesive layer 102 in the device opening frame 1013 [Fig. 2(c); p. 10, lines 4-9];
[4] laminating a second dielectric material to form a second dielectric layer 104, wherein the second dielectric layer 104 covers the metal frame 101 and fills the device opening frame 1013 and the via post opening frame 1012 [Fig. 2(d); p. 10, lines 11-20]; and
[5] forming a via post 1014 in the via post opening frame 1012 [Figs. 2(e)-(f); p. 10, line 28 to p. 11, line 3], and
[6] forming a first wiring layer 1052 and a second wiring layer 1062 which are conductively connected by the via post 1014 respectively on an upper surface and a lower surface of the second dielectric layer 104 [Figs. 2(e)-(f); p. 10, line 28 to p. 11, line 3].
With regard to features [1a]-[1b] and [2] of claim 1, the claimed “first dielectric” is not shown in Fig. 2(a) but is the mask used for the “pattern masking and etching” (p. 4, lines 24-26) used to form the openings 1012, 1013, as explained in Chen-713 (p. 9, lines 43-47; p. 13, lines 13-15). In this regard, Chen-713 states, “In some embodiments, the step (a) includes preparing the metal frame by punching, drilling and milling, or pattern masking and etching.” (p. 4, lines 24-26) and “Generally, the metal frame 101 can be prepared by punching, drilling and milling, or pattern masking [and] etching on the copper foil plate 1011.” (p. 9, lines 13-15)
Chen-713 does not state that the masking material is a dielectric. However, throughout the disclosure, photoresist is used to form patterned masks (e.g. at p. 4, lines 42-45) and “photosensitive insulating material”, e.g., for “core dielectric layer 104”, is patterned by “exposure and development” (e.g. at p. 10, lines 11-17) as shown in Fig. 2(d). In addition, the “photosensitive insulating material” is resistant to an etchant used to etch the metal seed layer 1042, as explained in Chen-713 (Figs. 2(f)-2(g); p. 11, lines 1-3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use at least a layer of photoresist or photosensitive insulating material as the claimed “first dielectric material” in Chen-713 because Chen-713 teaches that photoresist and photosensitive insulating patterned which are shown to be etch resistant to metal etchants, can be used to form patterned masks.
It is held, absent evidence to the contrary, that photoresist is also inherently electrically insulating, i.e. “dielectric”. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to features [4] and [6] of claim 1,
[4] laminating a second dielectric material to form a second dielectric layer, wherein the second dielectric layer covers the metal frame and fills the device opening frame and the via post opening frame; and
[6] forming a first wiring layer and a second wiring layer which are conductively connected by the via post respectively on an upper surface and a lower surface of the second dielectric layer.
It is noted that at least in the elected species in the Instant Application, the claimed second dielectric 102 is not formed on the lower face of the metal frame 1011 because the adhesive tape 1013 prevents this (Instant Application: Figs. 7B-7C). Hence the claim term, “cover”, does not require coverage of the lower face of the metal frame. As a result, the second wiring layer 1042(1041) that is “on … a lower surface of the second dielectric layer 102” is only on the lower surface portion of 102 that is exposed in the claimed “device opening frame” and “via post opening frame”, as shown in Figs. 7E-7F. Thus, Chen-713 has been interpreted consistent with that which is shown in the figures of the Instant Application.
This is all of the features of claim 1.
With regard to claim 2, Chen-713 further discloses,
2. The manufacturing method according to claim 1, wherein the first dielectric material [not shown] and the second dielectric material 104 are the same or different.
As explained above the first dielectric material can be photoresist or photosensitive insulating material, while the second dielectric material is photosensitive insulating material. Therefore, they can be the same or different.
With regard to claim 8, Chen-713 further discloses,
8. The manufacturing method according to claim 1, wherein the laminating of the first dielectric material [i.e. the photoresist or photosensitive insulating material (supra)] comprises forming a first feature pattern [i.e. the openings corresponding to the locations where holes 1012 and 1013 are etched] in the first dielectric layer by means of laser drilling, mechanical drilling, plasma etching, or exposure and development.
See discussion above under features [1a]-[1b] and [2] of claim 1.
With regard to claim 9, Chen-713 further discloses,
9. The manufacturing method according to claim 1, wherein the adhesive layer 102 in step (b) comprises an adhesive tape.
Chen-713 does not use the term “tape”, but shows and describes the adhesive layer 102 as adhesive tape, stating in this regard, “Generally, the adhesive layer 102 is a commercially available transparent film that can be decomposed by heat or can be decomposed by ultraviolet radiation” (p. 10, lines 6-7).
With regard to claims 10-11, Chen-713 further discloses,
10. The manufacturing method according to claim 1, wherein the applying of the adhesive layer 202 comprises attaching a terminal surface of the device 203 onto the adhesive layer 202 in the device opening frame 2013.
11. The manufacturing method according to claim 10, wherein the laminating of the second dielectric material 204 further comprises removing the adhesive layer 202 after laminating the second dielectric material 202 on a top surface of the metal frame to form the second dielectric layer [as shown in Figs. 4(d) and 4(g)-4(h)].
Chen-713 shows another embodiment in Figs. 3 and 4(a)-4(i) (p. 12, line 7 to p. 15, line 24) that teaches at of the features of claim 1 as well as “attaching a terminal surface of the device 203 onto the adhesive layer 202 in the device opening frame 2013” particularly as shown in Figs. 3 and Fig. 4(c).
With regard to claim 17, Chen-713 further discloses,
17. The manufacturing method according to claim 1, further comprising
[1] applying a first solder resist layer 109 and a second solder resist layer 110 on the first wiring layer 1051, 1052 and the second 1061, 1062 wiring layer, respectively, [Fig. 2(l); p. 11, lines 45-47] and
[2] treating an exposed metal surface [shown but not labeled] to form a solder resist window 1091, 1101 [Fig. 2(l); p. 11, line 45 to p. 12, line 5].
With regard to claims 18-20, the embodiments in each of Figs. 2(h)-(k) and Figs. 4(j)-(k) show a layer-increasing process on the bottom and top surfaces, respectively, including all of the limitations of claims 18-20,
18. The manufacturing method according to claim 1, further comprising: performing layer-increasing process on the first wiring layer 1061, 1062 [Figs. 2(h)-2(k)] and/or the second wiring layer 2051, 2052 [Figs. 4(h)-4(k)] to form an additional layer 1081, 1082 [Figs. 2(h)-2(k)], 2091, 2092 [Figs. 4(h)-4(k)] so as to form a multilayer interconnected structure.
19. The manufacturing method according to claim 18, wherein the additional layer comprises a dielectric layer 107 [Fig. 2(h)], 206 [Fig. 4(h) and a wiring layer 1081, 1082 [Figs. 2(h)-2(k)], 2091, 2092 [Figs. 4(h)-4(k)].
20. The manufacturing method according to claim 19, wherein the performing of the layer-increasing process further comprises
[1] applying a solder resist layer 110 [Fig. 2(l)], 210 [Fig. 4(l)] on an outermost side wiring layer 1081, 1082 [Figs. 2(h)-2(k)], 2091, 2092 [Figs. 4(h)-4(k)] and
[2] treating an exposed metal surface [shown but not labeled] to form a solder resist window 1091, 1101 [Fig. 2(l); p. 11, line 45 to p. 12, line 5], 2101, 2111 [Fig. 4(l); p. 15, lines 14-24].
D. Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-713, as applied to claims 1 and 2, above, and further in view of US 2021/0210427 (“Kang”) and as evidenced by US 5,257,000 (“Billings”) only for claim 5.
Claims 3-5 read,
3. The manufacturing method according to claim 2, wherein the first dielectric material and/or the second dielectric material comprises an inorganic filler reinforced polymer matrix.
4. The manufacturing method according to claim 3, wherein the polymer matrix is selected from polyimide, epoxy resin, bismaleimide triazine resin, polyphenylene ether, or a combination thereof.
5. The manufacturing method according to claim 3, wherein the inorganic filler is selected from a ceramic filler, a glass fiber, or a combination thereof.
The prior art of Chen-713, as explained above, teaches each of the features of claims 1 and 2.
Chen-713 does not disclose the composition of the first or second dielectric materials, the second dielectric material forming the core dielectric layer 104.
Kang, like Chen-713, teaches a semiconductor package including a semiconductor device 120 embedded in a dielectric layer 140 formed in an opening 111 in a core substrate 110a having wiring layers 160, 150 formed on upper and lower surfaces (Kang: ¶¶ 21-24; Figs. 2 and 4A-5B). Kang states that the dielectric layer 104 can be,
[0035] The encapsulant 140 may include an insulating material, for example, Ajinomoto Build-up Film (ABF), but embodiments are not particularly limited, and in some embodiments the encapsulant 140 may include other insulating materials. For example, the encapsulant 140 may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin including a reinforcing material such as an inorganic filler, specifically ABF, FR-4, BT, resin, or the like. In addition, molding materials such as an epoxy molding compound (EMC) or photosensitive materials such as a photoimageable dielectric (PID) may be used.
(Kang: ¶ 35; emphasis added)
FR-4 is known to be glass fiber as evidenced by Billings, stating “[a]n illustrative product known as FR-4 is based on glass fiber reinforced plastic. (See, Microelectronics Packaging Handbook, pp. 885-909, R. R. Tummala and E. J. Rymaszewski, ed., Van Nostrand Reinhold, N.Y. (1989)).” (Billings: col. 4, lines 36-40).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use any of the inorganic filler-reinforced resin materials taught in Kang as the second dielectric 104 in Chen-713 because Chen-713 is mere silent, such that one having ordinary skill in the art would use known materials suitable of the same purpose, such as the materials taught in Kang. As such, the claimed materials in claims 3-5 amount to obvious material choice. (See MPEP 2144.07.)
This is all of the features of claim 5.
Claim 6 reads,
6. The manufacturing method according to claim 3, wherein the polymer matrix is a photosensitive polymer resin.
Chen-713 states that the second dielectric layer, i.e. the “core dielectric layer 104 may include a photosensitive insulating material” (Chen-713: p. 8, 37-38) but does not give a composition.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the polymer matrix materials of the inorganic filler-reinforced resin materials taught in Kang to be photosensitive, because Chen-713 desires the “core dielectric layer 104 [to] include a photosensitive insulating material”.
This is all of the features of claim 6.
C. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen-713, as applied to claim 1, above, and further in view of US 2012/0229990 (“Adachi”).
Claim 7 reads,
7. The manufacturing method according to claim 1, wherein the laminating of the first dielectric material comprises roughening a surface of the copper foil.
The prior art of Chen-713, as explained above, teaches each of the features of claim 1.
Chen-713 does not teach that the copper foil 1011 is roughened before the patterning to form the openings and therefore before the pattern mask material, that is the “first dielectric” is laminated to the copper foil.
Adachi, like Chen-713, teaches a metal core substrate that may have a copper foil core 20 (Adachi: ¶¶ 33, 37; Fig. 7). Adachi further teaches that the copper foil surface is roughened to improve adhesiveness with the resin insulating layers 24, 25, 27 subsequently applied, thereto (id.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to roughen the copper foil 1011 before the patterning to form the openings and therefore before the pattern mask material, that is the “first dielectric” is laminated to the copper foil, in order to improve the adhesion of the first dielectric. As such, Adachi may be seen as an improvement to Chen-713 in this aspect. (See MPEP 2143.)
D. Claims 3-6 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-713, as applied to claims 1 and 2, above, and further in view of CN 112164677 A as evidenced by US 2022/0068760 (collectively “Chen-760”).
Although CN 112164677 A shares several common inventors and a common assignee with the Instant Application, CN 112164677 A published more than one year before the filing of the Instant Application and is therefore available as prior art under 35 USC 102(a)(1), and there exist no exceptions under 35 USC 102(b) to disqualify CN 112164677 A as prior art.
US 2022/0068760 is in the patent family of CN 112164677 A and is accordingly being used as a translation. As such, all citations to CN 112164677 A are from Chen-760.
Claim 13 reads
13. The manufacturing method according to claim 1, wherein the forming of the via post comprises:
[1] forming a via in the via post opening frame;
[2] depositing a first metal seed layer in the via and on the upper surface and the lower surface of the second dielectric layer;
[3] electroplating copper on the first metal seed layer, forming a via post in the via, and respectively forming a first copper layer and a second copper layer on the upper surface and the lower surface of the second dielectric layer;
[4] etching the first copper layer and the second copper layer to respectively form the first wiring layer and the second wiring layer; and
[5] etching the exposed first metal seed layer.
The prior art of Chen-713, as explained above, discloses each of the features of claim 1.
With regard to claims 13 and 16, Chen-713 further discloses,
13. The manufacturing method according to claim 1, wherein the forming of the via post 1014 comprises:
[1] forming a via 2012 in the via post opening frame [Fig. 2(d); “the core dielectric layer 104 can be partially removed by exposure and development to expose the positions of the terminals 1031 and the through holes 1012 of the device 103” (p. 10, lines 15-16)];
[2] depositing a first metal seed layer 1042 in the via and on the upper surface and the lower surface of the second dielectric layer 104 [Fig. 2(e); “a first metal seed layer 1042 is formed on the upper and lower surfaces of the core dielectric layer 104, the inner wall of the first metal frame opening 1041, and the inner wall of the through hole 1012” (p. 10, lines 22-25)];
[3] electroplating copper [p. 10, line 44] on the first metal seed layer 1042, forming a via post in the via 1014, and respectively forming a first copper layer 1051, 1052 and a second copper layer 1061, 1062 on the upper surface and the lower surface of the second dielectric layer 104 [Fig. 2(f); p. 10, lines 39-43];
[4] etching the first copper layer and the second copper layer to respectively form the first wiring layer and the second wiring layer; and
[5] etching the exposed first metal seed layer [Fig. 2(g); “Then, the first photosensitive dry film 1043 and the second photosensitive dry film 1044 are removed, and the exposed first metal seed layer 1042 is etched—step (g), as shown in FIG. 2(g).” (p. 11, lines 1-3)].
16. The manufacturing method according to claim 15, wherein the first metal seed layer comprises titanium, copper, titanium tungsten alloy, or a combination thereof [Chen-713: p. 10, lines 32-33: “metal seed layer may be copper, titanium or a combination thereof, preferably a combination of copper and titanium”].
With regard to feature [4] of claim 13 and claims 14-15,
[4] etching the first copper layer and the second copper layer to respectively form the first wiring layer and the second wiring layer; and
14. The manufacturing method according to claim 13, wherein the etching of the first copper layer and the second copper layer further comprises:
[1a] respectively applying a first photoresist layer and a second photoresist layer on the first copper layer and the second copper layer, and
[1b] patterning the first photoresist layer and the second photoresist layer to expose the first copper layer and the second copper layer;
[2] respectively etching exposed first copper layer and second copper layer to form the first wiring layer and the second wiring layer; and
[3] removing the first photoresist layer and the second photoresist layer.
15. The manufacturing method according to claim 13, wherein the first metal seed layer is deposited by means of electroless plating or sputtering.
Chen-713 does not teach that the first and second copper layers are etched, as required by feature [4] and claim 14, because their respective patterns are electroplated into openings in a photopatterned mask, as shown in Fig. 2(f) and as explained at page 10, lines 35-48.
Chen-713 does not clearly use the terms “electroless plating” or “sputtering” as the means of applying the seed layer in the via 1012 in the second dielectric layer 104, stating instead,
Generally, the first metal seed layer 1042 can be fabricated on the upper and lower surfaces of the core medium layer 104, the inner wall of the first metal frame opening 1041, and the inner wall of the through hole 1012 by chemical deposition or metal spraying. Preferably, the metal spray. The metal seed layer is made by splashing.
(Chen-713: p. 10, lines 28-32; emphasis added)
Chen-760, like Chen-713, teaches a semiconductor package including a semiconductor device 104 embedded in a dielectric layer 105 formed in an opening 1012 in a core substrate 101 having wiring layers 102, 103 formed on upper and lower surfaces (Chen-760: ¶¶ 68-70; Fig. 2).
Chen-760 further teaches that the wiring layers 102, 103 in the upper and lower surfaces of the substrate are formed by electroplating a blanket layer of copper on each of the upper and lower surfaces of the substrate, followed by etching to pattern the copper layers into the wiring layers 102, 103. In this regard, Chen-760 states,
[0084] depositing a first metal seed layer on the lower surface 101b of the support frame 101;
[0085] electroplating on the first metal seed layer to form a first metal layer;
[0086] applying a first photoresist layer on the first metal layer;
[0087] patterning the first photoresist layer to form a first feature pattern;
[0088] etching the first metal layer through the first feature pattern to form a heat dissipation layer 103, the heat dissipation layer 103 being in conductive connection with the first wiring layer 1013; and
[0089] removing the first etching stop layer and the first photoresist layer and etching away the first metal seed layer.
[0090] Generally, the first metal seed layer may be deposited on the lower surface 101b of the support frame 101 by an electroless plating or magnetron sputtering process; the first metal seed layer is copper or titanium or an alloy thereof.
[0092] applying a second etching stop layer on the heat dissipation layer 103;
[0093] depositing a second metal seed layer on the upper surface 101a of the support frame 101;
[0094] electroplating copper on the whole plate on the second metal seed layer to form a second metal layer;
[0095] applying a second photoresist layer such as a photosensitive dry film on the second metal layer;
[0096] patterning the second photoresist layer to form a second feature pattern;
[0097] etching the second metal layer through the second feature pattern to form a second wiring layer 102; and
[0098] removing the second etching stop layer and the second photoresist layer and etching away the second metal seed layer.
[0099] Generally, the second metal seed layer is copper or titanium or an alloy thereof;
[0100] the second metal seed layer may be deposited on the upper surface 101a of the support frame 101 by an electroless plating or magnetron sputtering process; ….
(Chen-760: ¶¶ 84-90 and 92-99; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to electrolessly plate or sputter deposit the seed layer 1042 of Chen-713 and to electroplate blanket copper layers and then etch the blanket copper layers into the wiring patterns on the upper and lower surfaces of the second dielectric 104 in Chen-713, i.e. to omit the patterned masks 1043 and 1062 of Chen-713, because Chen-760 teaches that (1) electroless plating and magnetron sputtering are suitable for forming metal seed layers of the same metals as used in Chen-713, i.e. Cu and Ti or alloy therefore, and (2) the blanket deposition and then etching process is suitable for the identical purpose of forming metallization layers on the upper and lower surfaces of the core substrate. As such the claimed process is merely the substitution of one known process for another known process—by the same inventors—to achieve the same resulting patterned copper features on the upper and lower surfaces of the core substrate. (See MPEP 2143.)
This is all of the features of claims 13-16.
V. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2010/0006330 (“Fu”) is cited for effectively teaching all of the features of claim 1 except for the first dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814