DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: the preamble of claim 11 is suggested to be changed to “A method for forming a resistive switching device, the method comprising:” for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin (US 2022/0328758).
Regarding claim 1, Yin discloses, in FIG. 13 and in related text, a resistive switching device, comprising:
a substrate;
a first dielectric layer (212) on the substrate;
a conductive via (213) in the first dielectric layer;
a bottom electrode (214) on the conductive via and the first dielectric layer;
a resistive switching layer (216) on the bottom electrode;
a spacer (220) covering a sidewall of the resistive switching layer and a sidewall of the bottom electrode (see Yin, [0011], [0016]-[0017]); and
a top electrode (253) capping the spacer and the resistive switching layer (see Yin, [0028], [0032]).
Regarding claim 2, Yin discloses the device of clam 1.
Yin discloses wherein the conductive via (213) comprises tungsten (see Yin, [0017]-[0018]).
Regarding claim 3, Yin discloses the device of clam 1.
Yin discloses wherein the bottom electrode (214) comprises TaN, TiN, Pt, Ir, Ru, or W (see Yin, [0018]).
Regarding claim 4, Yin discloses the device of clam 1.
Yin discloses wherein the top electrode (253) comprises TIN, TaN, Pt, Ir, or W (see Yin, [0031]-[0032]).
Regarding claim 8, Yin discloses the device of clam 1.
Yin discloses wherein the spacer (220) comprises silicon nitride (see Yin, [0018]).
Regarding claims 9-10, Yin discloses the device of clam 1.
Yin discloses a second dielectric layer (264) on the top electrode (253); and a contact (266) penetrating through the second dielectric layer and being electrically connected with the top electrode, wherein the contact is not in direct contact with the spacer (222) (see Yin, FIG. 13, [0036]-[0037]).
Claims 11-14 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin (US 2022/0328758).
Regarding claim 11, Yin discloses, in FIG. 13 and in related text, a method for forming resistive switching device, comprising:
providing a substrate;
forming a first dielectric layer (212) on the substrate;
forming a conductive via (213) in the first dielectric layer;
forming a bottom electrode (214) on the conductive via and the first dielectric layer;
forming a resistive switching layer (216) on the bottom electrode;
forming a spacer (220) covering a sidewall of the resistive switching layer and a sidewall of the bottom electrode (see Yin, [0011], [0016]-[0017]); and
forming a top electrode (253) capping the spacer and the resistive switching layer (see Yin, [0028], [0032]).
Regarding claim 12, Yin discloses the method of clam 11.
Yin discloses wherein the conductive via (213) comprises tungsten (see Yin, [0017]-[0018]).
Regarding claim 13, Yin discloses the method of clam 11.
Yin discloses wherein the bottom electrode (214) comprises TaN, TiN, Pt, Ir, Ru, or W (see Yin, [0018]).
Regarding claim 14, Yin discloses the method of clam 11.
Yin discloses wherein the top electrode (253) comprises TIN, TaN, Pt, Ir, or W (see Yin, [0031]-[0032]).
Regarding claim 18, Yin discloses the method of clam 11.
Yin discloses wherein the spacer (220) comprises silicon nitride (see Yin, [0018]).
Regarding claims 19-20, Yin discloses the method of clam 11.
Yin discloses forming a second dielectric layer (264) on the top electrode (253); and a contact (266) penetrating through the second dielectric layer and being electrically connected with the top electrode, wherein the contact is not in direct contact with the spacer (222) (see Yin, FIG. 13, [0036]-[0037]).
Claims 1-4 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutta (US 2023/0102165).
Regarding claim 1, Dutta discloses, in FIG. 9 and in related text, a resistive switching device, comprising:
a substrate;
a first dielectric layer (111) on the substrate;
a conductive via (125) in the first dielectric layer (see Dutta, FIG. 3, [0036]-[0039]);
a bottom electrode (122) on the conductive via and the first dielectric layer;
a resistive switching layer (123) on the bottom electrode;
a spacer (121) covering a sidewall of the resistive switching layer and a sidewall of the bottom electrode (see Dutta, FIG. 6, [0040]-[0041], [0045]); and
a top electrode (124, 135) capping the spacer (121) and the resistive switching layer (123) (see Dutta, FIGS. 6 and 9, [0041], [0048]-[0049]).
Regarding claim 2, Dutta discloses the device of claim 1.
Dutta discloses wherein the conductive via (125) comprises tungsten (see Dutta, [0033], [0039]).
Regarding claim 3, Dutta discloses the device of claim 1.
Dutta discloses wherein the bottom electrode (122) comprises TaN, TiN, Pt, Ir, Ru, or W (see Dutta, [0040]-[0041])
Regarding claim 4, Dutta discloses the device of claim 1.
Dutta discloses wherein the top electrode (124, 135) comprises TIN, TaN, Pt, Ir, or W (see Dutta, [0040]-[0041], [0048]).
Regarding claim 7, Dutta discloses the device of claim 1.
Dutta discloses wherein the spacer (121) has an L-shaped sectional profile (see Dutta, FIG. 6)
Regarding claim 8, Dutta discloses the device of claim 1.
Dutta discloses wherein the spacer (121) comprises silicon nitride (see Dutta, [0045]).
Claims 11-14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutta (US 2023/0102165).
Regarding claim 11, Dutta discloses, in FIG. 9 and in related text, a method for forming a resistive switching device, comprising:
providing a substrate;
forming a first dielectric layer (111) on the substrate;
forming a conductive via (125) in the first dielectric layer (see Dutta, FIG. 3, [0036]-[0039]);
forming a bottom electrode (122) on the conductive via and the first dielectric layer;
forming a resistive switching layer (123) on the bottom electrode;
forming a spacer (121) covering a sidewall of the resistive switching layer and a sidewall of the bottom electrode (see Dutta, FIG. 6, [0040]-[0041], [0045]); and
forming a top electrode (124, 135) capping the spacer (121) and the resistive switching layer (123) (see Dutta, FIGS. 6 and 9, [0041], [0048]-[0049]).
Regarding claim 12, Dutta discloses the method of claim 11.
Dutta discloses wherein the conductive via (125) comprises tungsten (see Dutta, [0033], [0039]).
Regarding claim 13, Dutta discloses the method of claim 11.
Dutta discloses wherein the bottom electrode (122) comprises TaN, TiN, Pt, Ir, Ru, or W (see Dutta, [0040]-[0041])
Regarding claim 14, Dutta discloses the method of claim 11.
Dutta discloses wherein the top electrode (124, 135) comprises TIN, TaN, Pt, Ir, or W (see Dutta, [0040]-[0041], [0048]).
Regarding claim 17, Dutta discloses the method of claim 11.
Dutta discloses wherein the spacer (121) has an L-shaped sectional profile (see Dutta, FIG. 6)
Regarding claim 18, Dutta discloses the method of claim 11.
Dutta discloses wherein the spacer (121) comprises silicon nitride (see Dutta, [0045]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dutta in view of Lee (US 2010/0038791).
Regarding claim 5, Dutta discloses the device of claim 1.
Dutta discloses the resistive switching layer (see discussion on claim 1 above).
Dutta does not explicitly disclose wherein the resistive switching layer comprises a hafnium oxide layer and a titanium layer.
Lee teaches wherein the resistive switching layer comprises a hafnium oxide (106) layer and a titanium layer (108) (see Lee, FIG. 3d, [0025]-[0026]).
Dutta and Lee are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Dutta with the features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Dutta to include wherein the resistive switching layer comprises a hafnium oxide layer and a titanium layer, as taught by Lee, in order to provide a resistive random access memory with stable binary resistance switching characteristics.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Dutta in view of Lee (US 2010/0038791).
Regarding claim 15, Dutta discloses the method of claim 11.
Dutta discloses the resistive switching layer (see discussion on claim 1 above).
Dutta does not explicitly disclose wherein the resistive switching layer comprises a hafnium oxide layer and a titanium layer.
Lee teaches wherein the resistive switching layer comprises a hafnium oxide (106) layer and a titanium layer (108) (see Lee, FIG. 3d, [0025]-[0026]).
Dutta and Lee are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Dutta with the features of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Dutta to include wherein the resistive switching layer comprises a hafnium oxide layer and a titanium layer, as taught by Lee, in order to provide a resistive random access memory with stable binary resistance switching characteristics.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the objection(s), set forth in this Office action and, in independent form including all of the limitations of the base claim and any intervening claims
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Dutta, discloses wherein the top electrode has an inverted U shaped sectional profile and covers a portion of a sidewall of the spacer. The prior art of records, individually or in combination, do not disclose nor teach “wherein the top electrode covers an entire sidewall of the spacer” in combination with other limitations as recited in claim 6 and claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811