DETAILED ACTION
This Office Action is in response to Amendment filed March 31, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: “the hard mask” should be replaced with “the patterned hard mask” on line 11 to avoid indefiniteness, and to be consistent with the limitation “the patterned hard mask” recited on line 7. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lidow et al. (US 2012/0175631) in view of Ota et al. (US 9,768,257)
Regarding claim 1, Lidow et al. disclose a method for fabricating high electron mobility transistor (HEMT) (Fig. 5), comprising: forming a first barrier layer (14 in Fig. 5a) ([0031]) on a substrate (11); forming a p-type semiconductor layer (15) ([0023]) on the first barrier layer; forming a hard mask (17 in Fig. 5b) ([0032]) on the p-type semiconductor layer, because (a) Applicants do not specifically claim what the hard mask is formed of, and (b) therefore, the gate metal 17 shown in Fig. 5b of Lidow et al. can be referred to as “a hard mask” since it is made of a hard material, and functions as a mask as shown in Fig. 5c of Lidow et al.; patterning the hard mask and the p-type semiconductor layer (Fig. 5c); forming a spacer (21 in Fig. 5e) ([0034]) adjacent to the patterned hard mask (17 in Fig. 5e) and the patterned p-type semiconductor layer (15 in Fig. 5e), wherein a top surface of the first barrier layer (14 in Fig. 5e) adjacent to two sides of the spacer is exposed after the spacer is formed (Fig. 5e), the spacer comprises an inner sidewall (sidewall in direct contact with patterned hard mask 17 and patterned p-type semiconductor layer 15) and an outer sidewall, and the outer sidewall of the spacer (21 in Fig. 5e) comprises a curve converging to a top surface of the hard mask; and forming a source electrode (20 in Fig. 5g) ([0036]) and a drain electrode (19) ([0036]).
Lidow et al. differ from the claimed invention by not comprising forming a gate electrode on the patterned hard mask.
Ota et al. disclose a method for fabricating a HEMT (Fig. 23), comprising forming a gate electrode (P1) (col. 26, line 32) on a patterned hard mask or another gate electrode (GE1) (col. 25, lines 62-63).
Since both Lidow et al. and Ota et al. teach a method for fabricating a HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method for fabricating HEMT disclosed by Lidow et al. can further comprise a step of forming a gate electrode on the patterned hard mask such as the first plug P1 shown in Fig. 23 of Ota et al., because (a) Applicants do not specifically claim what “a gate electrode” refers to, and therefore, any electrode or wiring such as the first plug P1 disclosed by Ota et al. that is electrically connected to another gate electrode, gate conductor, gate metal or conductive hard mask can be referred to as “a gate electrode” without Applicants’ specifically claiming what the gate electrode is formed of, and what it looks like, (b) in other words, unless Applicants claim that the claimed gate electrode is the only electrode disposed between a power supply and the patterned p-type semiconductor layer, any conductor or metal that allows biasing of a gate region that controls carrier movement of a channel region of the claimed HEMT can be referred to as “a gate electrode”, while the patterned gate metal 17 of Lidow et al. can be referred to as, for example, a first gate electrode, a lower gate electrode or a conductive hard mask, (c) as recited in claim 4, Applicants’ hard mask is formed of a conductive material, and therefore, Applicants’ patterned hard mask should also function as a gate electrode, and (d) the patterned gate metal layer 17 shown in Figs. 2 and 3E of Lidow et al. should be electrically connected to the outside world to control the carrier movement in the channel region of the HEMT, and it has been a common practice to form a plug or via that functions as a (part of a) gate electrode (stack) in semiconductor industry.
Regarding claim 2, Lidow et al. further comprise forming a buffer layer (12 and/or 13) ([0031]) on the substrate (11) before forming the first barrier layer (14).
Regarding claim 3, Lidow et al. in view of Ota et al. differ from the claimed invention by not further comprising: forming a second barrier layer on the first barrier layer adjacent to the spacer.
Ota et al. further comprise forming a second barrier layer (IL1 in Fig. 23) on a first barrier layer (ES).
Since both Lidow et al. and Ota et al. teach a method for fabricating HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Lidow et al. in view of Ota et al. can further comprise forming a second barrier layer on the first barrier layer adjacent to the spacer as disclosed by Ota et al., because (a) Applicants do not specifically claim what the second barrier layer is formed of and what it does, and (b) therefore, interlayer insulating film IL1 shown in Fig. 23 of Ota et al. can be referred to as “a second barrier layer” since (i) it is formed of an insulating material that has a band gap greater than a semiconductor material, and (ii) also, the interlayer insulating film IL1 would be able to function as a physical barrier against diffusion of unwanted impurities or contaminants into the channel layer to a certain degree.
Regarding claim 4, Lidow et al. further disclose that the hard mask (17) comprises a conductive material, because the hard mask is referred to as a “gate metal” by Lidow et al.
Regarding claim 7, Lidow et al. further disclose for the method of claim 1 that the first barrier layer (14; undoped AlGaN barrier material) comprises AlxGa1-xN.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Otake et al. (US 11,462,635)
Applicants' amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 May 19, 2026
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