DETAILED ACTION
This Office Action is in response to Amendment filed August 4, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lidow et al. (US 8,969,918) in view of Lidow et al. (US 8,404,508) (and further in view of Liu et al. (“Elimination of Gate Leakage in GaN FETs by Placing Oxide Spacers on the Mesa Sidewalls,” IEEE ELECTRON DEVICE LETTERS 34 (2013) pp. 1232-1234.)), further in view of Macelwee (US 10,985,259), still further in view of Cao et al. (US 9,748,347) and yet still further in view of Yoshida et al. (US 6,897,495) and Lee et al. (US 2012/0061727)
Regarding claim 1, Lidow et al. (US ‘918) disclose a high electron mobility transistor (HEMT) (Fig. 1), comprising: a buffer layer (6; Undoped Gallium Nitride); a first barrier layer (5; Aluminum Gallium Nitride) on the buffer layer; a p-type semiconductor layer (7; pGaN) on the first barrier layer; a hard mask (4; gate) on and covering an entire top surface of the p-type semiconductor layer, because (a) Applicants do not specifically claim what the hard mask is formed of, when it is employed as a hard mask, and what it does, and (b) therefore, the limitation “hard mask” is directed to an intended use of a layer that is disposed on the p-type semiconductor layer; and a spacer (8; dielectric) directly contacting a sidewall of the p-type semiconductor layer, because (a) Applicants do not specifically claim what the “spacer” refers to, what it is formed of, and/or what it does, and (b) Merriam-Webster dictionary defines “spacer” as “a device or piece used to create or maintain a desired amount of space (as between two parts)”, which is also the case with and a function of the Dielectric 8 disclosed by Lidow et al. (US ‘918), wherein the spacer comprises an inner sidewall and an outer sidewall, and the first barrier layer (5) comprises AlGaN.
Lidow et al. (US ‘918) differ from the claimed invention by not showing that the buffer layer is on a substrate, the hard mask comprises titanium nitride, a gate electrode is on the hard mask, wherein the gate electrode comprises gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), or palladium (Pd) and a width of the gate electrode is less than a width of a top surface of the hard mask, the outer sidewall of the spacer comprises a curve converging to a top surface of the hard mask, and by not comprising a second barrier layer adjacent to two sides of the spacer on the first barrier layer, wherein the second barrier layer comprise AlGaN.
Lidow et al. (US ’508) disclose a high electron mobility transistor (HEMT) (Figs. 4 and 5E), comprising: a buffer layer (13) (col. 4, lines 29-30) on a substrate (11) (col. 4, line 29), and a hard mask (17) comprising titanium nitride (col. 3, lines 39-44).
Since both Lidow et al. and Lidow et al. teach a high electron mobility transistor, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the buffer layer 6 disclosed by Lidow et al. (US ‘918) can be on a substrate as disclosed by Lidow et al. (US ‘508), and the gate metal or hard mask disclosed by Lidow et al. (US ‘918) can comprise titanium nitride as disclosed by Lidow et al. (US ‘508), because (a) a GaN buffer layer has been commonly formed on a substrate having the same material composition or a different material composition such that (i) the quality of the GaN buffer layer and subsequently deposited semiconductor layers can be improved by controlling and optimizing the epitaxial growth conditions of the GaN buffer layer and subsequently deposited semiconductor layers, (ii) other relatively cheap substrate materials can be employed, and (iii) other substrate materials having good thermal isolation characteristics or good thermal conductivities can be employed, (b) titanium nitride has been one of the most commonly employed gate metal or hard mask materials in forming a gate structure of a field effect transistor due to its high conductivity and its wide range of work function due to variability of the ratio of titanium and nitrogen in titanium nitride, and (c) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Further regarding claim 1, Lidow et al. in view of Lidow et al. differ from the claimed invention by not showing that a gate electrode is on the hard mask, wherein the gate electrode comprises gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), or palladium (Pd) and a width of the gate electrode is less than a width of a top surface of the hard mask, the outer sidewall of the spacer comprises a curve converging to a top surface of the hard mask, and by not comprising a second barrier layer adjacent to two sides of the spacer on the first barrier layer, wherein the second barrier layer comprise AlGaN.
Lidow et al. (US ‘508) further disclose a spacer (18 in Figs. 4 and 5E) (col. 4, lines 45-48) directly contacting a sidewall of the p-type semiconductor layer (21), wherein the outer sidewall of the spacer comprises a curve.
(In addition, Liu et al. disclose a high electron mobility transistor (HEMT) comprising a spacer (PETEOS in Figs. 2(a) and 2(b)), wherein the outer sidewall of the spacer comprises a curve.)
Since both Lidow et al. and Lidow et al. or Lidow et al./Liu et al. teach a high electron mobility transistor (HEMT), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the spacer (8; Dielectric) disclosed by Lidow et al. (US ‘918) can comprise an outer sidewall that comprises a curve as disclosed by Lidow et al. (US ‘508) (and Liu et al.), because (a) Fig. 1 of Lidow et al. (US ‘918) illustrates a schematic diagram of the HEMT, whose outer wall of the spacer (8; Dielectric) would likely have an outer sidewall comprising a curve as disclosed by Lidow et al. (US ‘508) (and Liu et al.) since, in a real semiconductor device structure, no layer would have a perfectly rectangular shape or an angled shape such as the Dielectric 8 shown in Fig. 1 of Lidow et al. (US ‘918), and (b) rather, forming a layer such as the spacer or the Dielectric 8 shown in Fig. 1 of Lidow et al. (US ‘918) to have a perfectly rectangular shape or an angled shape would be harder, if not impossible, to form and would cost more than the layer or the spacer comprising a curved outer sidewall shown in Lidow et al. (US ‘508) (and Liu et al.).
In this case, the curve disclosed by Lidow et al. (US ‘508) (and Liu et al.) implemented in the HEMT disclosed by Lidow et al. (US ’918) would converge to a top surface of the hard mask (4 of Lidow et al. (US ‘918)), because Fig. 1 of Lidow et al. (US ‘918) shows that the edges of the top surface of the hard mask (4; Gate) and the edges of the top surface of the spacer (8; Dielectric) meet and contact with each other.
Still further regarding claim 1, Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) differ from the claimed invention by not showing that a gate electrode is on the hard mask, wherein the gate electrode comprises gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), or palladium (Pd) and a width of the gate electrode is less than a width of a top surface of the hard mask, and by not comprising a second barrier layer adjacent to two sides of the spacer on the first barrier layer, wherein the second barrier layer comprise AlGaN.
Macelwee discloses a HEMT (Fig. 9), comprising a buffer layer (306 or composite layer of 306 and 308), a first barrier layer (310a) on the buffer layer, a p-type semiconductor layer (316) (col. 9, line 3) on the first barrier layer, and a second barrier layer (310b) on the first barrier layer, wherein the first barrier layer and the second barrier layer comprise AlGaN (col. 9, lines 8-11).
Since both Lidow et al. (US ‘918) and Macelwee teach a HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the HEMT disclosed by Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) can further comprise the second barrier layer as disclosed by Macelwee, because (a) one of the embodiments shown in Fig. 6C of Macelwee is similar to that disclosed by Lidow et al. (US ‘918), and therefore, the barrier layer 5 in Fig. 1 of Lidow et al. (US ‘918), which is similar to the barrier layer 210 in Fig. 6C of Macelwee, can be replaced with the two-layer barrier structure as shown in Fig. 9 of Macelwee such that “The Al % and thickness of the first thickness of AlxGa1-xN barrier layer is selected to provide an appropriate threshold voltage Vth for E-mode operation” as disclosed on lines 15-17 of column 9 of Macelwee, and that “Thus, the threshold voltage is determined by the Al % under gate, and the resistance Rsg and Rgd determined by the Al % in the access regions, so that the threshold voltage Vth is decoupled from sheet resistance in access regions” as disclosed on lines 23-27 of column 9 of Macelwee, and (b) therefore, the two-layer barrier structure in Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) and further in view of Macelwee would allow forming a better semiconductor device structure with better electrical characteristics including a desired threshold voltage and desired resistances of Rsg and Rgd that can be independently optimized.
In this case, the second barrier layer 310b of Macelwee would be adjacent to two sides of the spacer disclosed by Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) on the first barrier layer.
Still further regarding claim 1, Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) and further in view of Macelwee et al. differ from the claimed invention by not showing that and a gate electrode is on the hard mask, wherein the gate electrode comprises gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), or palladium (Pd) and a width of the gate electrode is less than a width of a top surface of the hard mask.
Cao et al. disclose a high electron mobility transistor (HEMT in Fig. 3A), comprising a gate electrode (vertical wiring for Vg in Fig. 3A) on a p-type semiconductor layer (P-TYPE MATERIAL) and a hard mask (GATE METAL).
Since both Lidow et al. (US ‘918) and Cao et al. teach a high electron mobility transistor (HEMT), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the HEMT disclosed by Lidow et al. (US ‘918) can further comprise a gate electrode on the p-type semiconductor layer and the hard mask as disclosed by Cao et al., because (a) Applicants do not specifically claim what the gate electrode refers to, what it is formed of, and what it looks like, and (b) the Gate 4 in Fig. 1 of Lidow et al. (US ‘918), which corresponds to the claimed hard mask, should be electrically connected to the outside world, for example, by the wiring disclosed by Cao et al. to form a functioning device.
Still further regarding claim 1, Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) and further in view of Macelwee et al. and still further in view of Cao et al. differ from the claimed invention by not showing that the gate electrode comprises gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), or palladium (Pd) and a width of the gate electrode is less than a width of a top surface of the hard mask.
Cao et al. appear to have shown that a width of the gate electrode (vertical wiring for Vg in Fig. 3A) is less than a width of a top surface of underlying layer.
In addition, Yoshida et al. disclose a HEMT (Fig. 1B), where a width of a gate electrode (40; (vertical portion of) wiring layer) (col. 7, line 2) is less than a width of a hard mask (32c) (col. 6, line 57).
Furthermore, Lee et al. disclose a high electron mobility transistor (HEMT), comprising a hard mask (G1) and a gate electrode (M3) on the hard mask, and a width of the gate electrode is less than a width of a top surface of the hard mask (G1).
Since both Lidow et al. and Cao et al., Yoshida et al. and Lee et al. teach a HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a width of the gate electrode disclosed by Cao et al. (vertical wiring for Vg in Fig. 3A) can be less than a width of the hard mask (4; gate) disclosed by Lidow et al. (US ‘918), because (a) a gate wiring layer, which corresponds to the claimed gate electrode, has been commonly formed to have a width less than a gate electrode, which corresponds to the claimed hard mask, which is also implied in Fig. 3A of Cao et al. with a width of the vertical wiring for Vg in Fig. 3A of Cao et al. being smaller than a width of the underlying structure, and (b) the gate wiring layer, which corresponds to the claimed gate electrode, does not need to be formed on the Dielectric 8 in Fig. 1 of Lidow et al. (US ‘918) such that the gate wiring layer would not create an unnecessary parasitic capacitance in the HEMT which would negatively affect the performance of the HEMT, see the illustration below; please note that the width of the wiring layer 40 of Yoshida et al. would be smaller than the minimum width of the hard mask 4 of Lidow et al., which is the width of the narrow top portion of the hard mask 4, as illustrated below since the shape of the hard mask 4 of Lidow et al. is different from the shape of the hard mask 32c of Yoshida et al.
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Still further regarding claim 1, Lidow et al. in view of Lidow et al. (and further in view of Liu et al.) and further in view of Macelwee et al. and still further in view of Cao et al. and still further in view of Yoshida et al. and Lee et al. differ from the claimed invention by not showing that the gate electrode comprises gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), or palladium (Pd).
Lee et al. further disclose that the gate electrode (M3) comprises gold (Au) ([0062]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gate electrode disclosed by Cao et al. can comprise gold (Au) as disclosed by Lee et al., because (a) gold has been one of the most commonly employed electrode or via materials in manufacturing semiconductor devices due to its high electrical conductivity, and (b) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Regarding claims 2, 3 and 7, Lidow et al. (US ‘918) in view of Lidow et al. (US ‘508) (and further in view of Liu et al.), further in view of Macelwee, still further in view of Cao et al. and yet still further in view of Yoshida et al. and Lee et al. further comprise the gate electrode (vertical wiring for Vg in Fig. 3A of Cao et al.) on the p-type semiconductor layer (7 of Lidow et al. (US ‘918)), and a source electrode (2 (Source) of Lidow et al. (US ‘918)) and a drain electrode (3 (Drain) of Lidow et al. (US ‘918)) adjacent to the two sides of the spacer (8 (Dielectric) of Lidow et al. (US ‘918)) (claim 2), wherein the hard mask (4; Gate in Fig. 1 of Lidow et al. (US ‘918)) is between the p-type semiconductor layer (7; pGaN in Fig. 1 of Lidow et al. (US ‘918)) and the gate electrode (vertical wiring for Vg in Fig. 3A of Cao et al.) (claim 3), and an upper portion of the spacer is narrower than the width of the gate electrode, because a width of the uppermost portion of the spacer converges to 0, see Fig. 2(c) of Liu et al. (claim 7).
Regarding claim 4, Lidow et al. (US ‘918) further disclose that the hard mask (4; Gate) comprises a conductive material, because the Gate 4 should be conductive, and Lidow et al. (US ‘508) discloses that the hard mask comprises titanium nitride as discussed above.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 12,100,756)
Bennerjee et al. (US 10,797,153)
Applicants' amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.K./Primary Examiner, Art Unit 2815 September 8, 2026
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