Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to claim 3 overcome the U.S.C. 112(b) rejection. Applicant's arguments filed 12/5/2025 have been fully considered but they are not persuasive. Applicant argues that the combination of Ganesan and Mahajan is not proper.
In response to applicant's argument that there is an incompatibly of process architectures, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, both references Ganesan and Mahajan are both in the inventor’s field of endeavor and pertinent to the problem with which the inventor is concerned.
In response to applicant's argument that Mahajan’s teaching is not a simple plug-in, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, one of ordinary skill in the art would be motivated to replace Ganesan’s polymer with an etched monolithic glass for the reason of providing mechanical robustness of the device, as discussed in the rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ganesan et al. (US Publication No. 2021/0305162) in view of Mahajan et al. (US Publication No. 2023/0317619).
Regarding claim 1, Ganesan discloses a chip high-density interconnection package structure comprising:
a glass carrier plate (630) having a groove (containing 100)
a glass frame (630 surrounding 100) surrounding the groove (100)
a first via post (611) penetrating the glass frame
a second via post (592) penetrating the groove
a first line layer (617 outer) and a second line layer (627 outer) formed on the upper and lower surfaces of the glass frame (630) and electrically connected via the first via post (611)
a third line layer (617 inner) and a fourth line layer (627 inner) formed on the upper and lower surfaces of the groove and electrically connected via the second via post (592)
a chip connection bridge (100) mounted on the third line layer in the groove
a fifth line layer (606) formed on the first line layer (617)
at least two chips (114-1/114-2) mounted on the second line layer (627 outer) and the fourth line layer (627 inner)
wherein the chip connection bridge (100) has a first pad (654), and the first pad is connected to the third line layer (617 inner) (Figure 6D), the terminals of the two chips (114) are each connected to the fourth line layer (627 inner) and/or the second line layer (627 outer) (Figure 6E), and the fifth line layer (606) is connected to the first line layer (617 outer) (Figure 6I)
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Ganesan does not disclose a glass grove formed locally by incompletely etching the glass carrier plate to a thickness less than the thickness of the glass frame. However, Mahajan discloses locally etching a glass carrier locally (paragraph 85). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Ganesan to include etching the glass carrier, as taught by Mahajan, since it can improve mechanical robustness of the device (paragraph 60).
Regarding claim 2, Ganesan discloses the chip connection bridge (110) further has a second pad (663) on an opposite surface of the first pad (654), wherein the second pad is connected to the fifth line layer (606) (Figure 6I).
Regarding claim 3, Ganesan discloses an encapsulation layer (617) covering the first circuit layer (611) and the connection bridge (100) (Figure 6E).
Regarding claim 4, Ganesan discloses an insulating layer (629) on the fifth line layer (606) and a sixth line layer (602) on the insulating layer (629). Element 602 can be interpreted to be “on” element 629 via element 606.
Regarding claim 5, Ganesan discloses the pitch of the first via posts (611) is greater than the pitch of the second via posts (592) (Figure 6B).
Regarding claim 6, Ganesan discloses the first pad (654) of the connection bridge (100) is connected to the third line layer (617 inner) by a conductive adhesive (paragraph 30). The metals of the first pad and third line layer are inherently conducive adhesives since they are adhered to each other. Additionally, Ganesan discloses the use of adhesive liners for conductive pathways (paragraph 30).
Regarding claim 7, Ganesan discloses the second line layer (627 outer) is on the same plane as the fourth line layer (327 inner); the first line layer (617 outer) is on the same plane as the second pad (663).
Regarding claim 8, Ganesan discloses the at least two chips (114-1/114-2) comprise a first chip (114-1) and a second chip (114-2), wherein terminals of the first chip and the second chip are connected to a part of the second line layer (627 outer) and a part of the fourth line layer (627 inner), respectively, so that the chip connection bridge (100) functions to connect the first chip and the second chip.
Regarding claim 9, Ganesan discloses a method for manufacturing a chip high-density interconnection package structure, the method comprising:
forming a groove (containing 100) and a glass frame (630) surrounding the groove (100), and forming a first via (611) and a second via (592) penetrating in a height direction on the glass frame and the groove
metalizing the glass carrier plate (630), forming a first line layer (617 outer) and a second line layer (627 outer) on the upper and lower surfaces of the glass frame (630), forming a third line layer (617 inner) and a fourth line layer (627 inner) on the upper and lower surfaces of the groove, filling the first via to form a first via post (611), filling the second via to form a second via post (592), so that the first via post is conductively connected to the first line layer (617 outer) and the second line layer (627 inner), and the second via post (592) is conductively connected to the third line layer (617 inner) and the fourth line layer (627 inner)
attaching a chip connection bridge (100) in the groove so that a first pad (654) of the chip connection bridge (100) is connected to the third line layer (617 inner)
laminating an encapsulation layer (617) so that the encapsulation layer covers the first line layer (617 outer) and the chip connection bridge (100)
forming a fifth line layer (606) on the encapsulation layer (617) so that the first line layer (617 outer) is connected to the fifth line layer (606)
forming an insulating layer (629) on the fifth line layer (606), and forming a sixth line layer (602) on the insulating layer (629), so that the fifth line layer (606) is connected to the sixth line layer (602)
flip-mounting at least two chips (114) on the second line layer and the fourth line layer (Figures 6E-6G)
wherein the at least two chips comprise a first chip (114-1) and a second chip (114-2), wherein terminals of the first chip and the second chip are connected to a part of the second line layer (627 outer) and a part of the fourth line layer (627 inner), respectively, so that the chip connection bridge (100) functions to connect the first chip (114-1) and the second chip (114-2)
Ganesan does not disclose locally etching the glass carrier plate to form the groove. However, Mahajan discloses locally etching a glass carrier incompletely to form a glass groove (paragraphs 70 and 85). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Ganesan to include etching a groove in a glass carrier, as taught by Mahajan, since it can improve mechanical robustness of the device (paragraph 60).
Regarding claim 10, Ganesan discloses the first pad (654) of the chip connection bridge (100) and the third line layer (617 inner) are fixed by a conductive adhesive connection (paragraph 30). The metals of the first pad and third line layer are inherently conducive adhesives since they are adhered to each other. Additionally, Ganesan discloses the use of adhesive liners for conductive pathways (paragraph 30).
Regarding claim 11, Ganesan discloses the chip connection bridge (110) further has a second pad (663) on an opposite surface of the first pad (654), wherein the second pad is connected to the fifth line layer (606) (Figure 6I).
Regarding claim 12, Ganesan discloses balling (354) on the sixth line layer (602) to form solder balls that lead through the at least two chips (114).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/N.R.P/ 1/1/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897