DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 6, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung’486 (US 6, 180, 486) in view of Leobandung’694 (US 6, 124, 694) and Nagano (US 2006/0234478).
Regarding claim 1, Leobandung’486 discloses a method for forming a mixed substrate, comprising the following steps: providing a silicon-on-insulator (SOI) silicon wafer (Fig.1, numerals 10-14), the SOI silicon wafer comprising a silicon substrate (10), a buried silicon oxide (BOX) (12) covering the silicon substrate (10), and SOI covering the BOX (12), depositing a layer of mask silicon oxide (16) on a silicon on insulator (SOI) the SOI silicon wafer, and then depositing a layer of mask silicon nitride (18) ; S2: performing dry etching to remove the mask silicon nitride, the mask silicon oxide, SOI, and buried silicon oxide (BOX) BOX above substrate silicon in the silicon substrate area (column 3, lines 63-67; Fig.2) ; oxidizing silicon on an upper surface of the substrate silicon in the silicon substrate area and on a side surface of an SOI area to form protective silicon oxide (Fig.3, numeral 28, 30; column 4, lines 4-15); performing etching to remove protective silicon oxide (28) on the substrate silicon (10) in the silicon substrate area, retaining protective silicon oxide (Fig. 5, numeral 30) on a side of the SOI and the BOX (14); and performing epitaxial silicon growth (Fig.6, 7, numeral 34) to enable the upper surface of the substrate silicon (10) in the silicon substrate area to grow flush with an upper surface of SOI (14) in the SOI area.
Leobandung’486 does not disclose (1) coating photoresist on the mask silicon nitride, and performing a photolithography process performing a photolithography process to open a silicon substrate area in which a silicon substrate is to be formed removing the photoresist; (2) depositing supplementary silicon oxide and that s supplementary silicon oxide is removed by performing etching and that the etching is a dry etching; (3) wherein shallow trench isolation (STI) is formed at a boundary between the SOI area and the silicon substrate area.
Regarding elements (1), Leobandung’486 discloses that trenches are created by conventional techniques such as masking and etching (column 3, lines 55-60). And Leobandung’694 discloses that trenches are created by coating photoresist on the mask silicon nitride, and performing a photolithography process performing a photolithography process to open a silicon substrate area in which a silicon substrate is to be formed removing the photoresist (column 3, lines 49-65).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Leobandung’486 with Leobandung’694 to performing coating photoresist on the mask silicon nitride, and performing a photolithography process performing a photolithography process to open a silicon substrate area in which a silicon substrate is to be formed removing the photoresist for the purpose of creation trenches.
Regarding element (2), Nagano discloses depositing supplementary silicon oxide (Fig. 1B, 1C numeral 92; 94 [0058]), and that supplementary silicon oxide (94) is removed by performing etching and that the etching is a dry etching; ([0059]; [0062]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Leobandung’486 with Nagano to deposit supplementary silicon oxide and that supplementary silicon oxide is removed by performing etching and that the etching is a dry etching for the purpose of improving growing process (Nagano, [0066]).
Regarding element (3), Leobandung’694 discloses wherein shallow trench isolation (STI) is formed at a boundary between the SOI area and the silicon substrate area (Figs. 2G, numeral 28C).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Leobandung’486 with), Leobandung’694 to form shallow trench isolation (STI) is formed at a boundary between the SOI area and the silicon substrate area for the purpose of fabrication an operational semiconductor device.
Regarding claim 4, Leobandung’486 in view of Leobandung’694 and Nagano does not disclose wherein a thickness of the supplementary silicon oxide is 4-20nm.
Nagano however discloses that the thickness of a supplemental silicon oxide is adjusted to form a sidewall protection film (Nagano, [0024]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to adjust the thickness of a supplementally silicon oxide to be in the claimed range for the purpose of optimization sidewall protection.
Regarding claim 5, Leobandung’486 discloses a thickness of the mask silicon oxide is 3-10nm (column 3, lines 50-52).
Leobandung’486 discloses does not disclose that a thickness of the mask silicon nitride is 10-30nm.
Leobandung’489 however discloses that the mask silicon nitride is used in creating trenches (column 3, lines 55-60).
It would have been however obvious to one of ordinary skill in the art at the time the invention was filed to adjust the thickness of the mask silicon nitride to be in the claimed range for the purpose of optimization an etching process.
Regarding claim 6, Nagano discloses after dry etching in step S7, wet cleaning is performed ([0063]) and then step S8 is performed ([0066]).
Regarding claim 8, Leobandung’694 discloses wherein, in step S5 a thickness of the protective silicon oxide formed by oxidizing the silicon on the upper surface of the substrate silicon in the silicon substrate area and the side surface of the SOI in the SOI area is 6-12nm (column 4, lines 9-16).
Regarding claim 9, Nagano discloses wherein, in step S7, dry etching is performed to remove silicon oxide in the silicon substrate area, and a lateral thickness of remaining silicon oxide on the side surface of the SOI in the SOI area is enabled to be greater than 3nm ([0065]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Leobandung’486 in view of Leobandung’694 and Nagano as applied to claim 1 above, and further in view of Assefa (US 2013/0277795).
Regarding claim 3, Leobandung’486 in view of Leobandung’694 and Nagano does not disclose wherein the supplementary silicon oxide is atomic layer deposition (ALD) silicon oxide.
Assefa however discloses depositing the supplementary silicon oxide by atomic layer deposition (ALD) silicon oxide ([0035]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Leobandung ‘486 with Assefa to have the supplementary silicon oxide is atomic layer deposition (ALD) silicon oxide because ADL is one of typical methods for forming oxide layers.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Leobandung’486 in view of Leobandung’694 and Nagano as applied to claim 1 above, and further in view of Nguyen (US 2009/0321872)
Regarding claim 7, Leobandung’694 discloses wherein, in step S5 the silicon on the upper surface of the substrate silicon in the silicon substrate area and the side surface of the SOI in the SOI area is oxidized to form the protective silicon oxide through an annealing process (column 4, lines 1-25; note: annealing).
Leobandung’694 does not disclose that annealing process is rapid thermal oxidation (RTO) process.
Nguyen however discloses annealing process could be performed as rapid thermal oxidation (RTO) process ([0046]).
It would have been therefore obvious to one or ordinary skill in the art at the time the invention was filed to modify Leobandung’694 with Nguyen to perform rapid thermal oxidation (RTO) process because this is one of the typical processes for annealing (Nguyen, [0046]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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