DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 1/7/2026, responding to the Office action mailed on 9/8/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are:
Claim 1 on page 2 (text printed on page) line 4 and claim 15 on page 3 (text printed on page) line 22 reference “the semiconductor layer”, but the claims do not introduce a semiconductor layer until page 2 line 5 for claim 1 and page 3 line 23 for claim 15.
For compact prosecution, the examiner interprets it to read:
…at least one source/drain electrode;
a semiconductor layer;
an adhesive layer directly contacting the at least one source/drain electrode and located between the at least one source/drain electrode and the semiconductor layer; and
at least one interfacial layer located…
Claims 2-14 & 16-17 are rejected as being dependent on claims 1 & 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1).
Itagaki teaches a transistor (FIG. 15), comprising:
at least one source/drain electrode (12 and 13) [0074];
a semiconductor layer (11);
an adhesive layer (16) [0076] directly contacting the at least one source/drain electrodes (12 and 13) and located between the at least one source/drain electrode (12 and 13) and the semiconductor layer (11).
Itagaki does not teach at least one interfacial layer located between the adhesive layer and the semiconductor layer;
wherein the at least one interfacial layer comprises a semiconducting material having a higher bond dissociation energy than indium oxide.
Ramaswamy teaches at least one interfacial layer (120a) [0035] located between the adhesive layer (adhesive layer in source/drain area (130) [0027], [0070] “In some embodiments, additional layers may be present in the source and drain contacts, such as adhesion layers…”) and the semiconductor layer (120c, [0047], FIG. 6D);
wherein the at least one interfacial layer (120a) comprises a semiconducting material (GaN) having a higher bond dissociation energy than indium oxide (GaN bond dissociation energy is over 378 kJ/mol based on attached file BDE2. Page 2 col 1 par 3 states, “Because the Ga-N bond dissociation energy is much higher compared to Ga-As [378 kJ mol-1 for (CH3)GaNH2…” BDE1 page 6 says indium oxide bond dissociation energy is 360 kJ/mol).
The ordinary artisan would have been motivated to modify Ramaswamy in combination with Itagaki in the above manner for the motivation of forming an interfacial layer between the semiconductor layer and the adhesive layer to help optimize the device performance and microwave frequencies. [0015] states, “The High Electron Mobility Transistor (HEMT) is a form of field effect transistor (FET) that is used to provide very high levels of performance at microwave frequencies.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ramaswamy into the structure of Itagaki.
Claims 2-4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Kim (US 20230209846 A1).
Re Claim 2 Itagaki in view of Ramaswamy teaches the transistor of claim 1, but does not teach the semiconducting material of the at least one interfacial layer comprises a metal-doped oxide semiconductor material, and is doped with Ga.
Kim teaches the semiconducting material of the at least one interfacial layer (ETL, [0058] “buffer layer”) comprises a metal-doped oxide semiconductor material (gallium (Ga)-doped zinc oxide).
The ordinary artisan would have been motivated to modify Kim in combination with Itagaki in view of Ramaswamy in the above manner for the motivation of metal doping the interfacial layer to achieve excellent electron mobility. [0059] states, “In- and Ga-doped ZnO (IGZO) is attracting attention due to having a wide bandgap, excellent electron mobility, high carrier concentration, and excellent light transmittance, and is used in inorganic thin film transistors (TFTs).”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Kim into the structure of Itagaki in view of Ramaswamy.
Re Claim 3 Itagaki in view of Ramaswamy and Kim teaches the transistor of claim 2, wherein the oxide semiconductor material (Kim, ETL) comprises ZnO [0058].
Re Claim 4 Itagaki in view of Ramaswamy and Kim teaches the transistor of claim 2, wherein the oxide semiconductor material (Kim, ETL, zinc oxide) is doped with Ga [0058].
Re Claim 15 Itagaki teaches a transistor (FIG. 15), comprising:
at least one source/drain electrode (12 and 13) [0074];
a semiconductor layer (11);
an adhesive layer (16) [0076] directly contacting the at least one source/drain electrode (12 and 13), and located between the at least one source/drain electrode and the semiconductor layer (11); and
Itagaki does not teach at least one interfacial layer located between the adhesive layer and the semiconductor layer;
Ramaswamy teaches at least one interfacial layer (120a) [0035] located between the adhesive layer (adhesive layer in source/drain area (130) [0027], [0070] “In some embodiments, additional layers may be present in the source and drain contacts, such as adhesion layers…”) and the semiconductor layer (120c, [0047], FIG. 6D);
The ordinary artisan would have been motivated to modify Ramaswamy in combination with Itagaki in the above manner for the motivation of forming an interfacial layer between the semiconductor layer and the adhesive layer to help optimize the device performance and microwave frequencies. [0015] states, “The High Electron Mobility Transistor (HEMT) is a form of field effect transistor (FET) that is used to provide very high levels of performance at microwave frequencies.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ramaswamy into the structure of Itagaki.
Itagaki in view of Ramaswamy does not teach the at least one interfacial layer comprises a metal-doped oxide semiconductor material.
Kim teaches the semiconducting material of the at least one interfacial layer (ETL, [0058] “buffer layer”) comprises a metal-doped oxide semiconductor material (gallium (Ga)-doped zinc oxide).
The ordinary artisan would have been motivated to modify Kim in combination with Itagaki in view of Ramaswamy in the above manner for the motivation of metal doping the interfacial layer to achieve excellent electron mobility. [0059] states, “In- and Ga-doped ZnO (IGZO) is attracting attention due to having a wide bandgap, excellent electron mobility, high carrier concentration, and excellent light transmittance, and is used in inorganic thin film transistors (TFTs).”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Kim into the structure of Itagaki in view of Ramaswamy.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Kim (US 20230209846 A1) as applied to claims 1 and 2 above, and further in view of Du et al. (KR 20140014546 A), Du2 hereafter.
Re Claim 5 Itagaki in view of Ramaswamy and Kim teaches the transistor of claim 2, but does not teach the metal comprises from about 0.1 to about 20 at% of the metal-doped oxide semiconductor material.
Du2 teaches in claim 18, “The atomic percentage of the indium to the oxide semiconductor material is at least 10 at% and at most 80 at%...”
The ordinary artisan would have been motivated to modify Du2 in combination with Itagaki in view of Ramaswamy and Kim in the above manner for the motivation of finding the ideal atomic percent values for the semiconductor layer and doping materials. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal atomic percent values.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Du2 into the structure of Itagaki in view of Ramaswamy and Kim.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1), as applied to claim 1 above and further, in view of Jong (VN 10030727 B).
Re Claim 6 Itagaki in view of Ramaswamy teaches the transistor of claim 1, but does not teach a metal layer or a metal oxide layer located between the adhesive layer and the semiconductor layer.
Jong teaches a metal layer or a metal oxide layer (280 contains titanium oxide, page 13 par 4) located between the adhesive layer (290, page 13 last par) and the semiconductor layer (211, page 15 par 2, figure of structure unlabeled and shown on page 48).
The ordinary artisan would have been motivated to modify Jong in combination with Itagaki in view of Ramaswamy in the above manner for the motivation of adding a metal/metal oxide layer between the semiconductor layer and the adhesive layer as the metal/metal oxide layer is conductive and will help optimize the current in the semiconductor device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jong into the structure of Itagaki in view of Ramaswamy.
Re Claim 18 Itagaki teaches a transistor (FIG. 15), comprising:
at least one source/drain electrode (12 and 13) [0074];
a semiconductor layer (11);
an adhesive layer directly (16) contacting the at least one source/drain electrode (12) and located between the at least one source/drain electrode (12 and 13) and the semiconductor layer (11); and
Ramaswamy teaches at least one interfacial layer (120a) [0035] located between the adhesive layer (adhesive layer in source/drain area (130) [0027], [0070] “In some embodiments, additional layers may be present in the source and drain contacts, such as adhesion layers…”) and the semiconductor layer (120c, [0047], FIG. 6D);
The ordinary artisan would have been motivated to modify Ramaswamy in combination with Itagaki in the above manner for the motivation of forming an interfacial layer between the semiconductor layer and the adhesive layer to help optimize the device performance and microwave frequencies. [0015] states, “The High Electron Mobility Transistor (HEMT) is a form of field effect transistor (FET) that is used to provide very high levels of performance at microwave frequencies.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ramaswamy into the structure of Itagaki.
Itagaki in view of Ramaswamy does not teach at least one metal or metal oxide layer located between the adhesive layer and the semiconductor layer.
Jong teaches at least one metal layer or a metal oxide layer (280 contains titanium oxide, page 13 par 4) located between the adhesive layer (290, page 13 last par) and the semiconductor layer (211, page 15 par 2, figure of structure unlabeled and shown on page 48).
The ordinary artisan would have been motivated to modify Jong in combination with Itagaki in view of Ramaswamy in the above manner for the motivation of adding a metal/metal oxide layer between the semiconductor layer and the adhesive layer as the metal/metal oxide layer is conductive and will help optimize the current in the semiconductor device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jong into the structure of Itagaki in view of Ramaswamy.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Jong (VN 10030727 B) as applied to claims 1 and 6 above, and further in view of Futase (US 10297312 B1).
Re Claim 7 Itagaki in view of Ramaswamy and Jong teaches the transistor of claim 6, but does not teach the metal oxide layer has a thickness of about 0.1 nm to about 20 nm.
Futase teaches the metal oxide layer (86, FIG. 3) has a thickness between 3nm and 60 nm (col 9 par 3).
The ordinary artisan would have been motivated to modify Futase in combination with Itagaki in view of Ramaswamy and Jong in the above manner for the motivation of finding optimal metal oxide layer thickness. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal metal oxide layer thickness.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Futase into the structure of Itagaki in view of Ramaswamy and Jong.
Re Claim 9 Itagaki in view of Ramaswamy and Jong teaches the transistor of claim 6, but does not teach the metal oxide layer comprises TiO2, W03, SnO2, RuO2, ScqO SrrCusO, or SrrTiwO, where 0 < q 1; 0< r 1; 0<s1; and 0 <w<1.
Futase teaches the metal oxide layer (86) comprises TiO2 (FIG.3 and 4, col 9 par 4 states, “the metal oxide layer 86 may be an insulating material, semiconducting material or electrically conductive material such as cobalt oxide, nickel oxide, vanadium oxide, stoichiometric titanium dioxide (TiO.sub.2)…”).
The ordinary artisan would have been motivated to modify Futase in combination with Itagaki in view of Ramaswamy and Jong in the above manner for the motivation of using a metal oxide layer to obtain desired chemical reactions during transistor production to build an optimal device. The abstract states, “…a metal oxide layer including an oxide of a metal element that provides a reversible chemical reaction under a bidirectional electrical bias at an interface with the barrier material layer.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Futase into the structure of Itagaki in view of Ramaswamy and Jong.
Claims 8, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Jong (VN 10030727 B) as applied to claims 1, 6, and 18 above, and further in view of Yamaguchi et al. (US 20070254455 A1).
Re Claim 8 Itagaki in view of Ramaswamy and Jong teaches the transistor of claim 6, but does not teach having a total of two interfacial layers, wherein the metal layer or metal oxide layer is located between the two interfacial layers.
Yamaguchi teaches having a total of two interfacial layers (101 and 103, “first insulating layer” and “second insulating layer”, respectively [0081]), wherein the metal layer (102) [0084] is located between the two interfacial layers (FIG. 5B).
The ordinary artisan would have been motivated to modify Yamaguchi in combination with Itagaki in view of Ramaswamy and Jong in the above manner for the motivation of adding two interfacial layers on each side of the metal layer to help optimize the current in the metal layer and in turn help the transistor function at peak performance.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yamaguchi into the structure of Itagaki in view of Ramaswamy and Jong.
Re Claim 19 Itagaki in view of Ramaswamy and Jong teaches the transistor of claim 18 but does not teach a total of two interfacial layers, wherein the at least one metal or metal oxide layer is located between the two interfacial layers.
Yamaguchi teaches a total of two interfacial layers (101 and 103, “first insulating layer” and “second insulating layer”, respectively [0081]), wherein the at least one metal (102) [0084] layer is located between the two interfacial layers (101 and 103, FIG. 5B).
The ordinary artisan would have been motivated to modify Yamaguchi in combination with Itagaki in view of Ramaswamy and Jong in the above manner for the motivation of adding two interfacial layers on each side of the metal layer to help optimize the current in the metal layer and in turn help the transistor function at peak performance.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yamaguchi into the structure of Itagaki in view of Ramaswamy and Jong.
Re Claim 20 Itagaki in view of Ramaswamy and Jong and Yamaguchi teaches the transistor of claim 18, wherein the at least one interfacial layer (Yamaguchi, 101) directly contacts the at least one metal (102) or metal oxide layer (FIG. 5B).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Jong (VN 10030727 B) as applied to claims 1, 6 above, and further in view of Li (CN 107240550 A).
Re Claim 10 Itagaki in view of Ramaswamy and Jong teaches the transistor of claim 6, but does not teach the metal layer has a thickness of about 10 nm to about 100 nm.
Li teaches the metal layer (15, page 6 par 4 and 5, FIG. 3) has a thickness of 20 A to 200 A (2 nm to 20 nm).
The ordinary artisan would have been motivated to modify Li in combination with Itagaki in view of Ramaswamy and Jong in the above manner for the motivation of finding optimal metal layer thickness. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal metal layer thickness.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Li into the structure of Itagaki in view of Ramaswamy and Jong.
Re Claim 11 Itagaki in view of Ramaswamy and Jong and Li teaches the transistor of claim 6, wherein the metal layer (Li, 15, FIG. 3) comprises Mg, Ca, Ga, Hf, Al (page 6 par 4), Sn, V, Ti, Cd, or Cu.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) as applied to claim 1 above, and further in view of Wu et al. (US 20160282975 A1).
Re Claim 12 Itagaki in view of Ramaswamy teaches the transistor of claim 1, but does not teach at least one interfacial layer comprises InxSntO, GayZnzO, InxGayZnzO, InxSntZnzO, InxSntTiwO, or InxSntGayZnzO, where 0 <t<1;0<w<1;0<x1;0<y1; and 0<z1.
Wu teaches at least one interfacial layer (transparent metal oxide layer) comprises indium gallium zinc oxide (IGZO) [0087].
The ordinary artisan would have been motivated to modify Wu in combination with Itagaki in view of Ramaswamy in the above manner for the motivation of using indium gallium zinc oxide for the interfacial layer to being stability to the device and optimize the transistor performance to peak levels.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Wu into the structure of Itagaki in view of Ramaswamy.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) as applied to claim 1 above, and further in view of Yao et al. (US 20220359708 A1).
Re Claim 13 Itagaki in view of Ramaswamy teaches the transistor of claim 1 but does not teach a lightly doped drain (LDD) region between the at least one interfacial layer and the semiconductor layer.
Yao teaches a lightly doped drain (LDD) (244) [0027] region between the at least one interfacial layer (252) [0028] and the semiconductor layer (222, [0017], FIG. 13).
The ordinary artisan would have been motivated to modify Yao in combination with Itagaki in view of Ramaswamy in the above manner for the motivation of having a lightly doped drain in the transistor device to help the channel region function at a pinnacle level. [0027] states, “…epitaxial source/drain features 244 include materials and/or dopants that achieve desired tensile stress and/or compressive stress in channel region 224.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yao into the structure of Itagaki in view of Ramaswamy.
Re Claim 14 Itagaki in view of Ramaswamy and Yao teaches the transistor of claim 1, but does not explicitly teach the at least one interfacial layer has a thickness of about 0.5 nm to ab1out 10 nm.
Yao teaches, “…interfacial layer 252 having a thickness t4 …t4 is about 2 nm to about 10 nm.
The ordinary artisan would have been motivated to modify Yao in combination with Itagaki in view of Ramaswamy and Yao in the above manner for the motivation of finding ideal interfacial layer thickness. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal interfacial layer thickness.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yao into the structure of Itagaki in view of Ramaswamy and Yao.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Kim (US 20230209846 A1) as applied to claim 15 above, and further in view of Kijima et al. (US 20070126042 A1).
Re Claim 16 Itagaki in view of Ramaswamy and Kim teaches the transistor of claim 15, but does not teach the metal-doped oxide semiconductor material has a higher bond dissociation energy than indium oxide.
Kijima teaches the metal-doped oxide semiconductor (50) [0095] and [0097] material (use titanium dioxide, BDE = 662 kJ/mol according to attached LUT) has a higher bond dissociation energy than indium oxide (BDE = 360 kJ/mol according to attached LUT).
The ordinary artisan would have been motivated to modify Kijima in combination with Itagaki in view of Ramaswamy and Kim in the above manner for the motivation of using a material with a high BDE to create a strong chemical bond in the device and ensure the transistor channels function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Kijima into the structure of Itagaki in view of Ramaswamy and Kim.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Itagaki et al. (US 20100109002 A1) in view of Ramaswamy et al. (US 20200219772 A1) and Kim (US 20230209846 A1) as applied to claim 15 above, and further in view of Jong (VN 10030727 B) and Yamaguchi et al. (US 20070254455 A1).
Re Claim 17 Itagaki in view of Ramaswamy and Kim teaches the transistor of claim 15, but does not teach a metal layer or a metal oxide layer located between the adhesive layer and the semiconductor layer.
Jong teaches a metal layer or a metal oxide layer (280 contains titanium oxide, page 13 par 4) located between the adhesive layer (290, page 13 last par) and the semiconductor layer (211, page 15 par 2, figure of structure unlabeled and shown on page 48).
The ordinary artisan would have been motivated to modify Jong in combination with Itagaki in view of Ramaswamy and Kim in the above manner for the motivation of adding a metal/metal oxide layer between the semiconductor layer and the adhesive layer as the metal/metal oxide layer is conductive and will help optimize the current in the semiconductor device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jong into the structure of Itagaki in view of Ramaswamy and Kim.
Itagaki in view of Ramaswamy and Kim and Jong does not teach the metal layer or the metal oxide layer directly contact the at least one interfacial layer.
Yamaguchi teaches the metal layer (102) [0084] directly contact the at least one interfacial layer (103, [0083], FIG. 4A).
The ordinary artisan would have been motivated to modify Yamaguchi in combination with Itagaki in view of Ramaswamy and Kim and Jong in the above manner for the motivation of optimally integrating the metal layer around the interfacial layer so the device can function at a peak level.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yamaguchi into the structure of Itagaki in view of Ramaswamy and Kim and Jong.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/
Primary Examiner, Art Unit 2818 6/5/26
Prosecution Insights