DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/14/2023 and 07/02/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 10, 11, 17, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2021/0098627 to Liaw (hereinafter Liaw).
Regarding Claim 1, Liaw discloses a method, comprising:
alternately forming a plurality of first and second semiconductor layers on a substrate; patterning the alternately formed first and second semiconductor layers into a plurality of stacks of semiconductor layers, the plurality of stacks being separate from each other by a space along a direction, and each of the stacks of semiconductor layers having a cross-sectional profile along the direction gradually widening towards the substrate (Fig. 6B);
forming an epitaxial feature in each of the spaces (208, Fig. 10B); and
removing the patterned second semiconductor layers from each of the stacks of semiconductor layers (Fig. 13B).
Regarding Claim 2, Liaw discloses the method of Claim 1, further comprising patterning the stack of semiconductor layers using an anisotropic plasma etch process [0026].
Regarding Claim 10, Liaw discloses the method of Claim 1, further comprising:
forming a plurality of sacrificial gate structures (210) on the first and second semiconductor layers before patterning the first and second semiconductor layers (Fig. 4B);
forming a conformal spacer (240, Fig. 5B) on a sidewall of each of the sacrificial gate structures; and
removing the stack of semiconductor layers exposed between the sacrificial gate structures by patterning the stack of semiconductor layers (Fig. 6B).
Regarding Claim 11, Cho discloses a method of forming void-free source/drain regions, comprising:
etching a stack of semiconductor layers on a substrate to form a space exposing the substrate, wherein the space has a cross-sectional profile that is gradually narrowing towards the substrate (Fig. 10A;
forming a first epitaxial layer at a bottom of the space (L1, Fig. 13); and
forming a second epitaxial layer over the first epitaxial layer in the space (L2).
Regarding Claim 17, Liaw discloses a semiconductor device structure, comprising:
a channel region, comprising:
a first channel layer (upper 220A, transistor 272; Fig. 27B) formed of a first material, wherein the first channel layer has a first width (L1); and
a second channel layer (middle 220A) formed of the first material and disposed below the first channel layer, wherein the second channel layer has a second width (unlabeled, greater than L1 and less than L2) greater than the first width;
a first source/drain feature (208) having a sidewall in contact with the first and second channel layers (Fig. 27B);
a gate dielectric layer (228) disposed to surround exposed surfaces of each of the first and second channel layers; and
a gate electrode layer (232) disposed on the gate dielectric layer.
Regarding Claim 18, Liaw discloses the semiconductor device structure of Claim 19, further comprising a third channel layer (lower 220A) formed of the first material below the second channel layer, wherein the third channel layer has a third width (L2) greater than the second width (Fig. 27B).
Regarding Claim 20, Liaw discloses the semiconductor device structure of Claim 18, wherein the source/drain feature has a gradually narrower profile from a top level of the first channel layer to a bottom level of the second channel layer (Fig. 27B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw as applied to Claim 1 above, and further in view of US PG Pub 2023/0059169 to Kim et al (hereinafter Kim).
Regarding Claim 9, Liaw discloses the method of Claim 1, further comprising alternately forming a plurality of Si layers and a plurality of SiGe layers on the substrate to form the stack of semiconductor layers [0018].
Liaw does not detail the concentrations of Ge in the SiGe layers.
Kim discloses alternating Si/SiGe layers wherein the SiGe layers have Ge concentrations gradually reduced from a bottom SiGe layer towards a top SiGe layer [0034].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the SiGe layer of Liaw such that the Ge concentrations gradually reduced from a bottom SiGe layer towards a top SiGe layer. The Ge concentration of a layer would have had known effects on the etching rate of a layer when using selective etching methods, resulting in a sloping side edge of the layer as portions having different Ge concentrations are etched at different rates.
Allowable Subject Matter
Claims 3-8, 12-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 and 12 require the patterning of the stack of semiconductor layers be performed by an etch process using a source power, a first bias power, and a second bias power at the same time. While the references disclose embodiments for source and bias powers, they do not disclose, or suggest, using a source power, a first bias power and a second bias power at the same time. Claims 4-8 and 13-16 depend on either Claims 3 or 12 and are allowable for at least the reasons above.
Claim 19 requires a plurality of additional channel layers formed of the first material below the second channel layers and either above or below the third channel layers, wherein the additional channel layers have widths gradually decreased from the second width. The references of record show that channels can vary in lengths such as increasing or decreasing with respect to a direction from the substrate and also show that the middle channel regions can have a width less than upper and lower channels, creating a bowing in shape for the semiconductor stack. However, the references do not disclose wherein the additional channel layers have widths gradually decreased from the second (and third) widths. This creates a bowing out effect for the channel stack similar to that seen in Fig. 5B of Applicant’s invention though Fig. 5B does lack the first three semiconductor layers as detailed by Claims 17 and 18.
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893