DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 03 April 2026, with respect to the 35 USC §112(a) rejections of claims 21-29, 35 USC §112(b) rejections of claim 20, and the 35 USC §103 rejections of claims 18-19, 30, 31-37 have been fully considered and are persuasive. Those rejections of 07 January 2026 have been withdrawn.
However, claim 21 does not define the features similar to previously indicated allowable claim 20 with sufficient specificity to overcome the prior art of record. The rejection is presented below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 28-29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 28, it recites “forming a cladding layer over the blocking structure and prior to forming the source/drain feature”. There is no support for this in the specification or figures for this claimed order of operations, because the claim requires the blocking structure for the formation of the cladding layer over said blocking structure. For at least this reason, claim 29 is also rejected under 35 USC 112(a) based on its dependency from claim 28.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 23, 25, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Veeraraghavan S. Basker et al. (US 2019/0189769 A1; hereinafter Basker) in view of Shogo Mochizuki et al. (US 2018/0358435 A1; hereinafter Mochizuki).
Regarding Claim 21, Basker teaches a method for forming a semiconductor device structure (Fig. 1A-1D {prior art figures} and 2A-2G, wherein the structure of Fig. 2A may be obtained in the same manner as described with reference to the prior art figures, wherein similar elements utilize the same reference numbers, as described in ¶0026), comprising:
forming a fin structure (fin shape of Fig. 1A) by patterning a stack of semiconductor layers (stack of 21/22 as shown in Fig. 1A), the stack comprising a plurality of first semiconductor layers (21) and a plurality of second semiconductor layers (22) alternatingly stacked (Fig. 1), wherein the first semiconductor layers and the second semiconductor layers have different etch selectivity (they have different etch selectivity being Si and SiGe which are different materials, commensurate in scope with the instant application [0023]);
forming a sacrificial gate structure (24; ¶0004) over a channel region of the fin structure (region containing channel layers 21; ¶0026);
forming a gate spacer (26; ¶0024) on sidewalls of the sacrificial gate structure (24) (Fig. 1B);
etching exposed portions of the fin structure (¶0004) to recess the fin structure adjacent to the sacrificial gate structure (as shown in Fig. 1C);
laterally etching a greater amount of the second semiconductor layers (22) relative to the first semiconductor layers (21) to form cavities (divots 27; ¶0004) at opposing ends of the second semiconductor layers (22 is etched at a greater amount relative to 21 which is not etched, wherein 27 is at opposing ends of 22 as shown in Fig. 1D/2A);
filling the cavities (27) with a dielectric material (dielectric material of 28; ¶0004) to form dielectric spacers (28) (Fig. 2A);
epitaxially forming a blocking structure (38; ¶0030-0032; formed of a doped semiconductor material which is commensurate in scope with the “blocking structure 141” of the instant application; and is doped and selectively grown from semiconductor 21 and not dielectric 28 as shown in Fig. 2C and ¶0031) on exposed end portions of the first semiconductor layers (21), the blocking structure (38) extending laterally to cover an interface between the sacrificial gate structure (24) and the gate spacer (26) (Fig. 2C);
epitaxially forming a source/drain feature (29; ¶0034) adjacent to the blocking structure (38) and the dielectric spacers (28) on opposite sides of the sacrificial gate structure (24) (Fig. 2E);
removing the sacrificial gate structure (24) and the second semiconductor layers (22) to expose sidewalls of the first semiconductor layers (21) (Fig. 2F); and
forming a gate electrode structure (32; ¶0039) to wrap around each of the exposed first semiconductor layers (21) (as shown in Fig. 2G).
Basker does not expressly disclose wherein the sacrificial gate structure (24) comprises a sacrificial gate dielectric and a sacrificial gate electrode layer,
wherein the blocking structure (38) extending laterally to cover an interface between the sacrificial gate dielectric layer and the gate spacer.
In the same field of endeavor, Mochizuki teaches a substantially similar device (Figs. 1-10); wherein a stack of alternating semiconductor layers (12/14; ¶0023) of a fin structure (FS1/FS2; ¶0024; ¶0028) which conforms to the profile of a sacrificial gate structure (16, 18; ¶0031-¶0035), wherein the sacrificial gate structure comprises a single sacrificial material layer (¶0031; such as in Basker above) or a stack of two or more sacrificial materials (¶0031) comprising a sacrificial gate dielectric and sacrificial gate material (¶0031) which are blanket deposited and then patterned to result in sacrificial gate portion 16 (as disclosed in ¶0034), wherein gate sidewall spacers (20; ¶0035) are formed on sidewalls of the patterned sacrificial gate portion (16, comprising the sacrificial gate dielectric and sacrificial gate material; as shown in Fig. 1).
Absent any evidence of criticality, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the sacrificial gate portion (16) of Mochizuki comprising the sacrificial gate dielectric and sacrificial gate material for the sacrificial gate structure of Basker (24) because they are art recognized equivalents (Mochizuki; ¶0031) for their intended same purpose of being a sacrificial gate structure (as explicitly disclosed in Mochizuki ¶0031-¶0035; see MPEP 2144.06 II).
This obvious substitution would result in Basker’s sacrificial gate structure (24) comprising a sacrificial gate dielectric layer and sacrificial gate electrode layer, wherein the blocking structure (38) extending laterally to cover an interface between the sacrificial gate dielectric layer and the gate spacer (an interface defined by the sides of sacrificial gate structure 24; Fig. 2C/2D).
Regarding Claim 23, modified Basker teaches the method of claim 22, wherein the boron-doped silicon germanium material has a dopant concentration in a range from about 5E20 atoms/cm3 to about 1 E22 atoms/cm3 (as modified by Mochizuki_2; ¶0044).
Regarding Claim 25, modified Basker teaches the method of claim 22, wherein the boron-doped silicon germanium material has a boron dopant concentration in a range of about 1 at.% to about 20 at.% (as modified by Mochizuki_2; ¶0044; commensurate in scope with the instant specification at [0052-0053]).
Regarding Claim 27, modified Basker teaches the method of claim 21, wherein the first semiconductor layers (21) comprise silicon and the second semiconductor layers (22) comprise silicon germanium (as labeled in the figures).
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Veeraraghavan S. Basker et al. (US 2019/0189769 A1; hereinafter Basker) in view of Shogo Mochizuki et al. (US 2018/0358435 A1; hereinafter Mochizuki) Shogo Mochizuki et al. (US 2021/0234020 A1; hereinafter Mochizuki_2).
Regarding Claim 22, modified Basker teaches the method of claim 21, but does not expressly disclose wherein epitaxially forming the blocking structure (38) comprises growing a boron-doped silicon germanium material.
In the same field of endeavor, Mochizuki_2 teaches a substantially similar GAAFET (Fig. 9 in view of Fig. 7), wherein doped epitaxial “blocking structures” (702; ¶0041) are grown from exposed portions of the channel layers (106; ¶0030) of the nanosheet stack (¶0030), wherein the silicon channel (¶0041-¶0045) has Si:B doped blocking structures (702; ¶0041) (as in Basker).
However, Mochizuki_2 teaches in ¶0041-¶0045 that the channel material and blocking structures can be selected equivalently to be a SiGe channel with boron doped SiGe “blocking structures” (702), wherein the sacrificial nanosheet layers (104) and the channel nanosheet layers (106) can alternately be selected (and are equivalent) as Si/SiGe or SiGe/Si depending on the desired device (¶0031-¶0033) while retaining etch selectivity (¶0048).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have SiGe as the material of the channel layers and SiGe doped with boron for the “doped blocking structures” in the device of modified Basker because of their art recognized equivalent for the same intended purpose (as outlined above with reference to Mochizuki_2; MPEP 2144.06 II).
With this obvious equivalent, wherein the channel layers (first semiconductor layers 21 of Basker being equivalently chosen in the manner of Mochizuki_2 to be SiGe), sacrificial semiconductor layers (second semiconductor layers 22 of Basker being equivalently chosen to be Si in the manner of Mochizuki_2) and doped blocking structure (38 of Basker being equivalently chosen to be SiGe:B in the manner of Mochizuki_2), the SiGe:B doped blocking structures would be formed with dopants included in-situ with precursors including boron and germanium (Mochizuki_2 ¶0044-¶0045) (Basker; ¶0031-¶0035).
Allowable Subject Matter
Claims 24 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 24, modified Basker teaches the method of claim 22. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the boron-doped silicon germanium material has a germanium concentration that gradually changes along a thickness of the blocking structure. The prior art of record teaches features relating to the boron doping concentration in the blocking structures, but does not disclose having a graded germanium concentration along a thickness of the blocking structures.
Regarding Claim 26, modified Basker teaches the method of claim 21, wherein laterally etching the second semiconductor layers comprises a selective wet etch process (¶0037).
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
Wherein the selective wet etch process removes the second semiconductor layers (22) by a first lateral distance greater than a second lateral distance by which the first semiconductor layers (21) are removed.
As shown in Basker Fig. 2A; 21 is not removed by any distance when performing the wet etch for recessing the second semiconductor layers (22) for the spacers (28), nor by the claimed distances.
Claims 18-19, and 30-37 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 18, the prior art of record teaches limitations as previously presented (see previous Office action). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
Wherein edge portions of the second semiconductor layers are removed by a first lateral distance and edge portions of the first semiconductor layers are removed by a second lateral distance less than the first lateral distance. As shown in Basker Fig. 2A; 21 is not removed by any distance when performing the etch for recessing the second semiconductor layers (22) for the spacers (28), nor by the claimed distances.
For at least this reason, claim 19 is also allowed.
Regarding Claim 30, the prior art of record teaches limitations as previously presented (see previous Office action). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
“… etching end portions of the first and second semiconductor layers …. , wherein edge portions of the second semiconductor layers are removed at a greater amount than that of the first semiconductor layers…”.
As shown in Basker Fig. 2A; 21 is not removed by any amount when performing the etch for recessing the second semiconductor layers (22) for the spacers (28), nor by the claimed amounts.
For at least this reason claims 31-37 are also allowed based on their dependency from claim 30.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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